Add support for MIPS32 and MIPS64 architectures:
- Remove all mmu-related code that may use 32 register on mips32-style implementatios and move them to mipsX_subr.S - which is then included from mips{3,32,64,5900}_subr.S with various control defines enabled. - Remove local cache instruction flags - Add badaddr64 (from Broadcom Corp).
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/* $NetBSD: mips32_subr.S,v 1.1 2002/03/05 15:50:59 simonb Exp $ */
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#undef MIPS1
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#undef MIPS3
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/* #undef MIPS32 */
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#undef MIPS64
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#undef MIPS3_4100
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#undef MIPS3_5900
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#include <mips/mips/mipsX_subr.S>
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/* $NetBSD: mips3_subr.S,v 1.1 2002/03/05 15:51:00 simonb Exp $ */
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#undef MIPS1
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/* #undef MIPS3 */
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#undef MIPS32
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#undef MIPS64
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#if 0 /* XXX separate mips3_4100.S?? */
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#undef MIPS3_4100
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#endif
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#undef MIPS3_5900
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#include <mips/mips/mipsX_subr.S>
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/* $NetBSD: mips5900_subr.S,v 1.1 2002/03/05 15:51:00 simonb Exp $ */
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#undef MIPS1
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/* #undef MIPS3 */
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#undef MIPS32
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#undef MIPS64
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#if 0 /* XXX separate mips3_4100.S?? */
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#undef MIPS3_4100
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#endif
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/* #undef MIPS3_5900 */
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#include <mips/mips/mipsX_subr.S>
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/* Toshiba R5900 specific functions */
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#include <mips/asm.h>
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#include <mips/cpuregs.h>
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.set noreorder
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.set mips3
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.text
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.align 6 /* align cache line size (64B) */
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/*
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* _intr_resume, _intr_suspend:
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* Fast interrupt locking functions.
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*/
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LEAF_NOPROFILE(_intr_resume)
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beqz a0, 1f
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nop
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ei
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1:
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j ra
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nop
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END(_intr_resume)
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LEAF_NOPROFILE(_intr_suspend)
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mfc0 v0, MIPS_COP_0_STATUS_REG
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lui t0, 0x1 /* EIE bit */
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and v0, v0, t0
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1: di
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sync.p
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mfc0 t1, MIPS_COP_0_STATUS_REG
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and t2, t0, t1
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beq t2, t0, 1b
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nop
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j ra
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nop
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END(_intr_suspend)
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/* $NetBSD: mips64_subr.S,v 1.1 2002/03/05 15:51:00 simonb Exp $ */
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#undef MIPS1
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#undef MIPS3
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#undef MIPS32
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/* #undef MIPS64 */
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#undef MIPS3_4100
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#undef MIPS3_5900
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#include <mips/mips/mipsX_subr.S>
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