Add support for MIPS32 and MIPS64 architectures:
- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead. - Add a command to dump cp0 state.
This commit is contained in:
simonb
parent
9b785c48f3
commit
c9a3bd8900
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@ -1,4 +1,4 @@
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/* $NetBSD: db_interface.c,v 1.40 2002/02/15 07:32:35 simonb Exp $ */
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/* $NetBSD: db_interface.c,v 1.41 2002/03/05 15:43:25 simonb Exp $ */
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/*
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* Mach Operating System
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@ -62,6 +62,7 @@ mips_reg_t kdbaux[11]; /* XXX struct switchframe: better inside curpcb? XXX */
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void db_tlbdump_cmd(db_expr_t, int, db_expr_t, char *);
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void db_kvtophys_cmd(db_expr_t, int, db_expr_t, char *);
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void db_cp0dump_cmd(db_expr_t, int, db_expr_t, char *);
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static void kdbpoke_4(vaddr_t addr, int newval);
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static void kdbpoke_2(vaddr_t addr, short newval);
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@ -321,7 +322,7 @@ db_tlbdump_cmd(db_expr_t addr, int have_addr, db_expr_t count, char *modif)
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{
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#ifdef MIPS1
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if (!CPUISMIPS3) {
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if (!MIPS_HAS_R4K_MMU) {
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struct mips1_tlb {
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u_int32_t tlb_hi;
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u_int32_t tlb_lo;
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@ -342,13 +343,19 @@ db_tlbdump_cmd(db_expr_t addr, int have_addr, db_expr_t count, char *modif)
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}
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}
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#endif
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#ifdef MIPS3
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if (CPUISMIPS3) {
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#ifdef MIPS3_PLUS
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if (MIPS_HAS_R4K_MMU) {
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struct tlb tlb;
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int i;
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for (i = 0; i < mips_num_tlb_entries; i++) {
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#if defined(MIPS3)
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mips3_TLBRead(i, &tlb);
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#elif defined(MIPS32)
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mips32_TLBRead(i, &tlb);
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#elif defined(MIPS64)
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mips64_TLBRead(i, &tlb);
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#endif
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db_printf("TLB%c%2d Hi 0x%08x ",
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(tlb.tlb_lo0 | tlb.tlb_lo1) & MIPS3_PG_V ? ' ' : '*',
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i, tlb.tlb_hi);
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@ -385,9 +392,144 @@ db_kvtophys_cmd(db_expr_t addr, int have_addr, db_expr_t count, char *modif)
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printf("not a kernel virtual address\n");
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}
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#define FLDWIDTH 10
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#define SHOW32(reg, name) \
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do { \
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uint32_t __val; \
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\
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asm volatile("mfc0 %0,$" ___STRING(reg) : "=r"(__val)); \
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printf(" %s:%*s %#x\n", name, FLDWIDTH - strlen(name), "", __val); \
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} while (0)
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/* XXX not 64-bit ABI safe! */
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#define SHOW64(reg, name) \
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do { \
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uint64_t __val; \
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\
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asm volatile( \
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".set push \n\t" \
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".set mips3 \n\t" \
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".set noat \n\t" \
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"dmfc0 $1,$" ___STRING(reg) " \n\t" \
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"dsll %L0,$1,32 \n\t" \
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"dsrl %L0,%L0,32 \n\t" \
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"dsrl %M0,$1,32 \n\t" \
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".set pop" \
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: "=r"(__val)); \
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printf(" %s:%*s %#llx\n", name, FLDWIDTH - strlen(name), "", __val); \
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} while (0)
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void
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db_cp0dump_cmd(db_expr_t addr, int have_addr, db_expr_t count, char *modif)
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{
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SHOW32(MIPS_COP_0_TLB_INDEX, "index");
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SHOW32(MIPS_COP_0_TLB_RANDOM, "random");
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if (!MIPS_HAS_R4K_MMU) {
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SHOW32(MIPS_COP_0_TLB_LOW, "entrylow");
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} else {
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if (CPUIS64BITS) {
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SHOW64(MIPS_COP_0_TLB_LO0, "entrylo0");
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SHOW64(MIPS_COP_0_TLB_LO1, "entrylo1");
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} else {
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SHOW32(MIPS_COP_0_TLB_LO0, "entrylo0");
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SHOW32(MIPS_COP_0_TLB_LO1, "entrylo1");
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}
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}
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if (CPUIS64BITS) {
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SHOW64(MIPS_COP_0_TLB_CONTEXT, "context");
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} else {
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SHOW32(MIPS_COP_0_TLB_CONTEXT, "context");
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}
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if (MIPS_HAS_R4K_MMU) {
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SHOW32(MIPS_COP_0_TLB_PG_MASK, "pagemask");
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SHOW32(MIPS_COP_0_TLB_WIRED, "wired");
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}
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if (CPUIS64BITS) {
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SHOW64(MIPS_COP_0_BAD_VADDR, "badvaddr");
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} else {
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SHOW32(MIPS_COP_0_BAD_VADDR, "badvaddr");
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}
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if (cpu_arch >= CPU_ARCH_MIPS3) {
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SHOW32(MIPS_COP_0_COUNT, "count");
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}
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if (CPUIS64BITS) {
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SHOW64(MIPS_COP_0_TLB_HI, "entryhi");
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} else {
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SHOW32(MIPS_COP_0_TLB_HI, "entryhi");
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}
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if (cpu_arch >= CPU_ARCH_MIPS3) {
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SHOW32(MIPS_COP_0_COMPARE, "compare");
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}
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SHOW32(MIPS_COP_0_STATUS, "status");
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SHOW32(MIPS_COP_0_CAUSE, "cause");
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if (CPUIS64BITS) {
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SHOW64(MIPS_COP_0_EXC_PC, "epc");
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} else {
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SHOW32(MIPS_COP_0_EXC_PC, "epc");
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}
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SHOW32(MIPS_COP_0_PRID, "prid");
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SHOW32(MIPS_COP_0_CONFIG, "config");
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#if defined(MIPS32) || defined(MIPS64)
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if (CPUISMIPSNN) {
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uint32_t val;
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val = mipsNN_cp0_config1_read();
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printf(" config1: %#x\n", val);
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}
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#endif
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if (MIPS_HAS_LLSC) {
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if (CPUISMIPS64) {
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SHOW64(MIPS_COP_0_LLADDR, "lladdr");
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SHOW64(MIPS_COP_0_WATCH_LO, "watchlo");
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} else {
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SHOW32(MIPS_COP_0_LLADDR, "lladdr");
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SHOW32(MIPS_COP_0_WATCH_LO, "watchlo");
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}
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SHOW32(MIPS_COP_0_WATCH_HI, "watchhi");
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if (CPUIS64BITS) {
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SHOW64(MIPS_COP_0_TLB_XCONTEXT, "xcontext");
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}
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if (CPUISMIPSNN) {
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if (CPUISMIPS64) {
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SHOW64(MIPS_COP_0_PERFCNT, "perfcnt");
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} else {
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SHOW32(MIPS_COP_0_PERFCNT, "perfcnt");
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}
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}
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SHOW32(MIPS_COP_0_ECC, "ecc");
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SHOW32(MIPS_COP_0_CACHE_ERR, "cacherr");
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SHOW32(MIPS_COP_0_TAG_LO, "cachelo");
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SHOW32(MIPS_COP_0_TAG_HI, "cachehi");
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if (CPUIS64BITS) {
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SHOW64(MIPS_COP_0_ERROR_PC, "errorpc");
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} else {
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SHOW32(MIPS_COP_0_ERROR_PC, "errorpc");
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}
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}
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}
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const struct db_command db_machine_command_table[] = {
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{ "kvtop", db_kvtophys_cmd, 0, 0 },
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{ "tlb", db_tlbdump_cmd, 0, 0 },
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{ "cp0", db_cp0dump_cmd, 0, 0 },
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{ (char *)0, }
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};
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#endif /* !KGDB */
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