3f5be1863e
srmmu cache flush: use to the CPU context parameter; this is now required.
2003-01-03 09:19:03 +00:00
0cff9e28dc
Checkpoint of O2 work by Chris Sekiya and myself. This is the sgimips bit;
...
still needs some arch/mips support code before it will fully work.
2003-01-03 09:09:21 +00:00
b983746705
Also remove `options MIPS3_5200' since nothing uses it ATM.
2003-01-03 08:18:20 +00:00
2d6f1ac150
The Tigon driver is known to have issues on BE systems, so remove it (I got
...
the card probed & attached, but had to hack the driver source to even get
it that far and it had issues after that which made me punt on it).
2003-01-03 08:14:44 +00:00
f2c485b280
Move console setup after we've determined machine type so the console init
...
code can guess where to find a console depending on machine type.
2003-01-03 06:26:06 +00:00
fe84d50d7e
Mark the CRIME/MACE register twiddling done after autoconfig with an XXX so
...
it gets cleaned out when the interrupt registration code is capable of doing
the interrupt mask setup itself.
2003-01-03 06:24:18 +00:00
285679b875
Added new ioctl command, WSMOUSEIO_GETID to tell touch panel identifier
...
for tpctl(8).
2003-01-03 04:36:26 +00:00
81c6d35e2b
Remove obsolete MACHINE_ARCH -> arm32
2003-01-03 02:40:57 +00:00
c2e9de7319
Don't define -D${MACHINE} in Makefile.arm. Instead, let platforms
...
that care define it themselves. Note that evbarm NO LONGER defines
-D${MACHINE}.
2003-01-03 02:34:48 +00:00
bc45f5ceeb
Split board-specific Makefile fragments into their own files.
2003-01-03 02:16:26 +00:00
e5afd96a97
Use the common linker script for all evbarm platforms.
2003-01-03 02:02:11 +00:00
b179f9cf73
Use the generic irq_dispatch.S
2003-01-03 00:55:59 +00:00
6620220d46
Use the generic irq_dispatch.S
2003-01-03 00:41:19 +00:00
074858daeb
Fiddle with current_intr_depth in assembly code again. Because we
...
have just pushed a frame, we can make some assumptions that the
compiler cannot as easily make, and can thus do it slightly more
efficiently.
2003-01-03 00:38:16 +00:00
6c9c7f3b21
Garbage-collect prev_intr_depth; nothing uses it.
2003-01-02 23:54:39 +00:00
b33e60be39
Clean up evbarm interrupt support a little:
...
* Define an ARM_INTR_IMPL option, which specifies a header file
describing the interrupt implementation for the platform. Use
this instead of the list of EVBARM_BOARDTYPE checks.
* Make the s3c2xx0 interrupt dispatch code a bit more generic, and move
it to a generic location so that other platforms can use it.
This eliminates all uses of the EVBARM_BOARDTYPE stuff, so delete it.
2003-01-02 23:37:53 +00:00
147ab60754
Enable a few more bus_space functions.
...
If a region is outside the regular obio space in obio_bs_map(), create
mappings for it.
2003-01-02 23:04:08 +00:00
9f57359336
Don't need to explicitly include <arm/s3c2xx0/s3c2xx0_intr.h>.
2003-01-02 22:30:04 +00:00
fb4bf2a901
* tweak CRIME and MACE interrupt masks for IP32 and add some verbosity
...
* recognize ahc scsi as a boot device
once again thanks to Chris Sekiya
2003-01-02 15:08:18 +00:00
050140988d
Add commented out entry for acpi(4).
2003-01-02 12:36:51 +00:00
c79ff46cb6
don't try to setup MXCC registers on non-primary CPU's on systems without
...
SMP support.
2003-01-02 09:42:09 +00:00
c065f11230
Oeps... forgot the versions file
2003-01-02 01:05:35 +00:00
6bf498b3c2
A little more debug.
2003-01-01 21:00:42 +00:00
f2a72b5110
Make sure DDB is set up correctly when we have SYMTAB_SPACE.
2003-01-01 16:18:49 +00:00
256784b520
Set up proper symbol table space.
2003-01-01 16:18:03 +00:00
9dd42c6155
SMP: lock kernel for soft interrupts < IPL_SCHED as well.
2003-01-01 16:17:10 +00:00
a89cd41b68
Add NEED_SYMTAB to run dbsym.
2003-01-01 16:14:36 +00:00
3607bd7dca
pmap_alloc_cpu: use flags from boot cpu for now, as the passed cpu_info
...
structure has not been fully setup yet.
2003-01-01 15:56:11 +00:00
16305a65cb
prom mailbox map: look for the property `mailbox-virtual' first.
2003-01-01 15:51:00 +00:00
79037114d8
this file is really no longer used
2003-01-01 08:41:17 +00:00
2fff4ee989
fix a comment.
2003-01-01 08:24:48 +00:00
62a9b2484d
this is no longer used.
2003-01-01 07:45:41 +00:00
aa9a4f85dd
enable sab & sabtty
2003-01-01 07:45:21 +00:00
d06249b555
KNF.
2003-01-01 06:33:29 +00:00
98b0e9af47
Use aprint_normal() for cfprint routines.
2003-01-01 02:31:13 +00:00
9c1214153c
Use aprint_normal() for cfprint routines.
2003-01-01 02:20:47 +00:00
dca15fc8c2
Use aprint_normal() for cfprint routines.
2003-01-01 02:10:08 +00:00
95fa2e148a
Use aprint_normal() for cfprint routines.
2003-01-01 01:57:51 +00:00
dbb0f0ebed
Use aprint_normal() for cfprint routines.
2003-01-01 01:47:30 +00:00
72a2c87923
Use aprint_normal() for cfprint routines.
2003-01-01 01:34:45 +00:00
1132348b98
Use aprint_normal() for cfprint routines.
2003-01-01 01:24:19 +00:00
359ed65495
Use aprint_normal() for cfprint routines.
2003-01-01 00:46:13 +00:00
1eab093085
* Use a device node for each DMA channel.
...
* Use aprint_normal() for cfprint routines.
2003-01-01 00:45:00 +00:00
21fbbf679c
Define a base for each DMA channel.
2003-01-01 00:44:34 +00:00
7ca7bdb37c
Use aprint_normal() for cfprint routines.
2003-01-01 00:39:19 +00:00
41a403fb33
Use aprint_normal() for cfprint() routines.
2003-01-01 00:35:30 +00:00
a7f53c4d06
Use aprint_normal() for cfprint routines.
2003-01-01 00:34:05 +00:00
aec1389b37
Use aprint_normal for cfprint routines.
2003-01-01 00:32:04 +00:00
5001cdaf1f
Use aprint_normal() for cfprint routines.
2003-01-01 00:25:01 +00:00
703e7687a9
Use aprint_normal() in cfprint routines.
2003-01-01 00:16:46 +00:00
0ad39e91ea
Fix sysmon entry.
2002-12-31 22:43:38 +00:00
2aac3c7c89
Slight optimisation in proc_trampoline().
2002-12-31 17:07:36 +00:00
1df04e663f
Make the schedintr() code common for all timers.
2002-12-31 16:45:52 +00:00
7b7269ba42
New version of cpu_switch/switchexit, mostly to simplify SMP support. It's
...
currently conditional on ALT_SWITCH_CODE (defaults to `on' if MULTIPROCESSOR
is defined) until more testing rounds are completed.
2002-12-31 16:17:12 +00:00
3d8def4865
Use a soft interrupt scheme to schedule schedclock(), so we can make
...
splsched() less than splhigh().
2002-12-31 15:57:26 +00:00
67e16e38a4
Define IPL_SCHED at level 11 and make splsched() use it.
2002-12-31 15:51:18 +00:00
d358537b64
Pass the CPU context to all TLB flush routines. Because of this (and the
...
fact that cache flushes are also passed the context number), most
"long-term" context switches can be eliminated from the SRMMU versions
of the pmap functions.
2002-12-31 15:23:29 +00:00
83dae8a821
* map the PROM CPU mailbox if available.
...
* map MXCC error/status registers if available.
* add MXCC-specific module error interrupt handler.
* use high priority interrupt level in mp_pause_cpus()
2002-12-31 15:10:28 +00:00
2b59d26892
Add offset for `cpuinfo.ci_tt'.
2002-12-31 15:05:48 +00:00
c3bb05ff5b
* Add level argument to raise_ipi()
...
* Add diagnostic field members to cpu_info.
2002-12-31 15:04:49 +00:00
5c671fd10d
nmi_sun4m: run handler at splhigh()
2002-12-31 14:34:54 +00:00
43b86d0b59
rwindow debug code: display the current cpu number.
2002-12-31 13:17:23 +00:00
a1e9e5cae8
Add some more definitions: SRMMU and MXCC reset register.
2002-12-31 12:01:27 +00:00
031dbfcca0
add PCI bus access device.
2002-12-31 06:54:13 +00:00
4b995bb9a4
fix for my sony laptop, which doesn't quite follow spec
2002-12-30 21:55:05 +00:00
006384eaed
In the case there is just one SIMM and one memory bank from the SIMM things
...
got wrong when no VRAM was there.
Placing the video DRAM in front of the kernel is OK when its 1Mb since the
kernel wants to be on a Mb boundary. Placing the video DRAM in the last
SIMM bank at the front is also OK unless there is just one SIMM and just one
bank; then it got in the way again!
Solution is to put the DRAM at the end of the SIMM instead of the beginning!
This however can result in the non 16 kb alignment of the top of physical
RAM where the temporary L1 page tables are situated. If its not 16 kb aligned
then move the L1 page table address down and down until it is 16 kb aligned.
This memory will be reused later on anyway.
What to do when we really support changing screensizes... see it as a max?
or use a different sceme alltogether? It might not even be a bootloader
problem then allthough its memory is not showing up in the DRAM/VRAM
block counts wich needs to be fixed one day.
2002-12-30 15:54:46 +00:00
2f6fe363fa
Since we dont support switching screenmodes (yet) we might as well claim
...
just enough for the screenmemory to be in instead of the maximum of 1Mb.
Small machines like my 8Mb NC get a 700 kb back and thats really noticeable.
2002-12-30 03:30:16 +00:00
3e5225eafa
If we don't have VRAM then at least account the screensize correctly :) it goes
...
pretty wierd if it is set wrongly.
2002-12-30 02:19:20 +00:00
33ae7765a1
If we nick memory from the DRAM for video then please account it correctly!
2002-12-30 02:05:12 +00:00
f223d87792
Typo and comments
2002-12-29 22:41:08 +00:00
d4ed18b479
Block tty interrupts in getc()/putc().
2002-12-29 20:12:19 +00:00
17fa1f0778
- X pads bitmap rows to a word boundary.
...
- Handle WSDISPLAYIO_GCURMAX.
2002-12-29 20:01:17 +00:00
9d1bcdf947
Use "__asm" instead of "asm" to pacify lint.
2002-12-29 14:41:29 +00:00
d320ba3418
Use "__asm __volatile" instead of "asm volatile" to pacify lint.
2002-12-29 14:40:35 +00:00
069c964473
Do not try to return a value from void functions.
2002-12-29 14:38:11 +00:00
7bc5ebdb72
Wrap DELAY() macro with do { } while (/*CONSTCOND*/ 0).
2002-12-29 14:09:37 +00:00
a391e8bea6
Add sh7709 INTEVT2 codes for IRQs, PINTs, IRDA and ADC.
2002-12-29 02:47:07 +00:00
24dac6bf26
The unique machine ID is used in some networking stuff to generate a
...
unique-ish number, so better add it again!
2002-12-29 00:30:40 +00:00
bf5fbfa164
Update the NetBSD part for the bootloader change. Mostly the changes in
...
bootconfig.h needs reflection
2002-12-29 00:02:20 +00:00
46dbb0f225
Initial commit of the 3rd generation of bootloaders for the Acorn32
...
platform. It features far better support for newer architectures and is
fully rewritten in C and compile-able under NetBSD.
Since it shares code with `boot26' for Acorn26 merging the common parts is
likely to be next on the list.
2002-12-28 23:57:36 +00:00
d2a5a7fd71
Regen.
2002-12-28 22:13:22 +00:00
e946acdd50
Since 1.6 we have 3 images (not 2!):
...
- 1Mb on HD floppy's
- 1.44Mb on HD floppy's
- 1.44Mb on a DD floppy
2002-12-28 22:11:30 +00:00
779842e0f8
Remove spurious declaration of bootconfig structure since that is already
...
done in bootconfig.h
2002-12-28 20:40:21 +00:00
20d271e712
TODO list, paraphrasing Jason Thorpe
2002-12-28 20:12:24 +00:00
2ae40935fb
The correct way to decorate objects with attributes is to use __attribute__
...
instead of the synonyms understood by gcc.
2002-12-28 20:11:57 +00:00
f69bc61a87
remove redundant declaration
2002-12-28 20:06:07 +00:00
8eb0fffdfc
Add an npx at acpi(4) attachment
2002-12-28 17:51:16 +00:00
13e7cd4f3f
Use i386_isa_chipset explicitly.
2002-12-28 17:36:59 +00:00
df719d72e4
NACPCA -> NACPI, so isa_dmainit gets called if we have ACPI support too.
2002-12-28 17:31:25 +00:00
6b5d7a7b6c
Remember the isa_chipset_tag_t and supply to isa_intr_establish.
...
(thereby removing a XXX in the code).
2002-12-28 17:13:39 +00:00
51ec27c813
Move the call to isa_dmainit to mainbus_attach from pnpbios_attach since
...
ACPI needs to have that done for the exact same reasons as ACPI.
2002-12-28 17:11:50 +00:00
e60823f9f2
Fix typo in comment.
2002-12-28 16:52:02 +00:00
46cc633768
Oops, fix typo in the previous.
2002-12-28 16:44:43 +00:00
bca1052dab
on second thought... make this also compile
2002-12-28 16:44:36 +00:00
00ddd0deec
add timer calibration
...
from Chris Sekiya
2002-12-28 16:40:48 +00:00
da446ea2da
Change device names in struct pica_dev to match ones used by ARC BIOS.
...
All of these parameters should be obtained from ARC BIOS, and we will
switch to the way in future. As per discussion with soda.
2002-12-28 16:25:38 +00:00
c8111254a1
Pass ISA chipset information through to ACPI devices, to allow for porting
...
of pnpbios(4) glue to acpi(4).
2002-12-28 06:14:07 +00:00
ca70f10e3b
Add the loadfile_machdep.h as needed for native bootloaders
2002-12-28 02:42:13 +00:00
122353da40
rename CPU_READY() to CPU_NOTREADY() seeing that's what it checks.
2002-12-28 02:35:56 +00:00
7d51aacb32
update the vme bus_space_tag_t to reality.
2002-12-28 01:33:00 +00:00
5a1aba72d6
Bump SYMTAB_SPACE to 190000.
2002-12-27 14:59:21 +00:00
fbc8e4748a
Add support for SEGA LAN Adapter, MB86967 based Ethernet adapter.
...
Based on the patches in port-dreamcast/17493 by Christian Groessler,
with several modification by me.
2002-12-27 11:43:38 +00:00
c680050521
Add a set of bus_space(9) functions for g2bus devices with
...
sparse address space. This is required for SEGA LAN adapter support.
2002-12-27 11:34:05 +00:00
f464631d66
Several things:
...
1) rights should be shared by the threads within a process. While it would
be easier to handle this with the struct proc/struct lwp split, we attempt to
do this now by sharing the right lists. Because each right holds a reference
to struct proc, this might cause some problems later.
2) in pthread_exit, really exit the thread. Also reintialize the righ tlist to
make sure we will not destroy the parent's right list
3) rights can hold multiple permissions on a port (ie: send and receive). Fix th
is.
4) first attempt on right carried by messages. We still have to do rights carrie
d in the message body (complex messages).
2002-12-27 09:59:24 +00:00
30d4a8344b
sync with mecreg change, ie. make this compile
2002-12-26 22:25:12 +00:00
a0c298e366
brush up situation with mec register definitions
...
from Chris Sekiya
2002-12-26 22:24:46 +00:00
c99132ebb0
Shuffle network interface and phy drivers into alphabetical order and
...
add comments for them.
2002-12-26 18:26:07 +00:00
ffbcb6d927
Conditionalize T_DBPAUSE trap handling on #ifdef MULTIPROCESSOR to make
...
single CPU kernels compile again.
2002-12-26 12:14:31 +00:00
9f582c3342
Cosmetic changes to reduce diff against GENERIC.
2002-12-26 08:25:20 +00:00
41313fe244
#<space>comment...
...
Pointed out by collver1 via PR#18468.
2002-12-26 08:21:56 +00:00
89143201f7
add db_dump_itlb.
2002-12-25 22:24:56 +00:00
70bd8bf51e
new function dump_itlb.
2002-12-25 22:05:10 +00:00
580c60b346
When scanning HP keyboard, disable output on all scan lines except the
...
one we are currently scanning. This is what Hitachi's sample WinCE
code does. Thanks to YAEGASHI Takeshi for pointing this out!
This makes same row chords work properly, most importantly
Ctrl-@, Ctrl-W, Ctrl-S, Ctrl-Alt-F1 (ctrl row), Ctrl-Alt-F3 (alt row).
2002-12-24 11:49:03 +00:00
87a74ecee8
Use crimereg.h definitions for the crime dog. Also, move watchdog
...
disable down the very last possible place in cpu_reboot.
from Chris Sekiya
2002-12-23 21:04:23 +00:00
8ecf5692ac
add bus_space_vaddr()
...
from rafal
2002-12-23 20:41:47 +00:00
0dd7013e7a
MACE register definitions
...
from Chris Sekiya
2002-12-23 20:05:06 +00:00
b31b740c2b
CRIME register definitions
...
from Chris Sekiya
2002-12-23 20:04:22 +00:00
1fcaee0848
add debug printf
...
from Rafal
2002-12-23 19:49:27 +00:00
2f32342d20
also create boot.ip32 with the entry point set to the IP32 load address
...
from Chris Sekiya
2002-12-23 19:31:24 +00:00
fb83173bb6
add some ethernet interfaces
...
from Chris Sekiya
2002-12-23 19:18:34 +00:00
fa3da541f9
update for added ktrsyscall() argument
...
XXX this should probably be converted to use trace_enter()/trace_exit(),
XXX the current code doesn't support systrace
2002-12-23 16:26:13 +00:00
f8055a350c
* Use correct PC value for displaying the called function.
...
* Merge code to display non-kernel frames.
2002-12-23 13:21:10 +00:00
1bfd32c4f3
Fix pasto in comment.
2002-12-23 09:59:25 +00:00
f953a01835
xcallintr() receive a `clockframe *' argument, not a `trapframe *'.
...
Setup a DDB context for paused CPUs by defining a soft trap (T_DBPAUSE)
which uses the generic trap handler code to get the trapframe constructed
and then calls on a debugger-defined `suspend' routine.
2002-12-23 00:55:16 +00:00
5c62f82bdf
Upon trap exit, update the trapframe with data for the running CPU rather
...
than the one which was the last target of the `machine cpu' command.
2002-12-23 00:42:37 +00:00
ea577b210e
Debugging is usually spelled with three gs.
2002-12-22 13:50:35 +00:00
7bda39e405
Use generic_bs_wr_4 for writing region
2002-12-22 11:28:37 +00:00
2c9ff5a338
Use generic_bs_sr_4
2002-12-22 11:24:07 +00:00
6ee482ef5b
change what 'hw.model' reports to be more inline with other netbsd ports, as
...
well as reporting the actual machine model & cpu, rather than first configured
CPU. changes for two machines are:
old:
hw.model = TMS390Z50 v0 or TMS390Z55 @ 75 MHz, on-chip FPU
hw.model = SUNW,UltraSPARC @ 143.002 MHz, version 0 FPU
new:
hw.model = SUNW,SPARCstation-20 (TMS390Z50 v0 or TMS390Z55 @ 75 MHz, on-chip FPU)
hw.model = SUNW,Ultra-1 (SUNW,UltraSPARC @ 143.002 MHz, version 0 FPU)
as per discussion on port-sparc & port-sparc64.
2002-12-22 02:17:24 +00:00
85dbe5f6c5
Make the DMA controller a separate device attached to intio. Intio
...
devices can use the DMA controller too.
2002-12-22 00:17:13 +00:00
75851dc4ed
Make this compile with LOCK_DEBUG
2002-12-22 00:11:10 +00:00
4a06119a9d
Pass the system call table to trace_enter() and ktrsys() so that it is
...
possible to use alternate system call tables. This is usefull for
displaying correctly the arguments in Mach binaries traces.
If NULL is given, then the regular systam call table for the process is used.
2002-12-21 16:23:56 +00:00
4e0634669b
* xcallintr(): use cpuinfo directly again.
...
* nmi_soft(): remove most of the obsoleted requests.
2002-12-21 12:55:54 +00:00
0408b1cbc8
tlb_flush_segment() and tlb_flush_region() now take a virtual address
...
argument instead of segment and region numbers.
2002-12-21 12:52:55 +00:00
82815de0ad
Use xcall() to broadcast MMU TLB flushes.
2002-12-21 12:13:38 +00:00
8dcde9f5b1
* cpu_hatch(): enable interrupts upon return from cpu_setup().
...
* interrupt trap: acquire the kernel lock only for interrupt levels <= PIL_SCHED
2002-12-21 11:57:41 +00:00
1d8dc4daf2
* getcacheinfo_obp(): also initialise the cacheinfo i/d associativity fields
...
in the case of a unified cache.
* xcall(): slightly optimise the `wait for other CPUs' loop.
2002-12-21 11:48:55 +00:00
899e58abe7
Bump ramdisk size to 2920 blocks.
2002-12-20 23:14:14 +00:00
738ea71fdd
Remove __P().
2002-12-20 16:54:15 +00:00
2cac3aae2d
Remove __P().
2002-12-20 16:39:10 +00:00
0687b33b99
Remove __P().
2002-12-20 16:23:46 +00:00
4e87eae834
Use Software Single Stepping for now when PPC_IBM4xx is defined. The
...
existing hardware assisted method doesn't work on this cpu.
Also correct the "I_B" constant in db_machine.h.
2002-12-20 15:23:12 +00:00
9e1fd4dd36
Driver for keyboard controller in the SA-1111 companion chip.
...
Our PC keyboard driver (sys/dev/pckbc/pckbd.c) works only with 8042
keyboard controller driver (sys/dev/ic/pckbc.c). So, This file
provides same functions as those of 8042 driver.
XXX: we need cleaner interface between the keyboard driver and
keyboard controller drivers.
XXX: PS/2 mice are not supported yet.
2002-12-20 04:12:51 +00:00
7b1d3e8b2b
comment out a file that is not in the tree yet.
2002-12-20 01:10:11 +00:00
2a39e8388d
Merge the IBM 4xx into the common powerpc/locore_subr.S, and
...
eliminate all the duplicated context switch related code in
the IBM 4xx port.
2002-12-19 19:37:25 +00:00
a6dc36fa4e
Build LKMs with -msoft-float.
2002-12-19 19:36:26 +00:00
f0a20f1305
* mark selected fields of `struct xpmsg' as volatile, instead of the whole
...
structure.
* change volatile => __volatile
2002-12-19 16:31:38 +00:00
c10c20ac28
Add a range check for the DCR address in db_ppc4xx_dcr().
2002-12-19 13:45:03 +00:00
de98ba0a49
Add a "machine dcr" command, for the IBM4XX case, which permits
...
reading/writing of the cpu's DCR registers.
2002-12-19 13:29:53 +00:00
2fba4e01ff
Mark CPUs that did not spin up properly and don't enable them later on.
2002-12-19 11:20:30 +00:00
75c5f270d2
Brush-up the generic cross-call routine and use it to implement the SMP
...
cache flush ops.
Also a standard soft interrupt handler for standard cross-call notification
reserving the NMI level 15 softint for urgent cross calls.
2002-12-19 10:38:28 +00:00
eaf530d598
Sprinkle volatiles to avoid register allocation, esp. in cross-call
...
synchronisation functions used in SMP kernels.
2002-12-19 10:30:39 +00:00
ec2b1c3c64
smp_cache_flush() also takes a context parameter.
2002-12-19 10:27:19 +00:00
1b5acb64d0
Initialize the media to 10baseT. From Steph Bailey.
2002-12-19 07:15:05 +00:00
2076dbdb04
Install the sparc V8 multiply/divide routines after we've collected some
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basic information on the CPUs.
2002-12-18 11:56:43 +00:00
1a854929dd
we use nmi_hard and nmi_soft on SUN4D as well
2002-12-18 06:20:36 +00:00
b757504104
Config information for Intel PXA2xx application processors.
2002-12-18 05:47:31 +00:00
ee778f8dfa
config staff for Lubbock
2002-12-18 04:56:52 +00:00
5f7d2415b6
back out a part of my previous commit.
2002-12-18 04:25:56 +00:00
7e91daa3b3
guard against being included twice
2002-12-18 04:20:36 +00:00
35345c15f5
+ protect against including twice
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+ add struct sa1111_attach_args for keyboard controller support.
2002-12-18 04:16:09 +00:00
b454cbf9c6
+ protect against including twice
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+ add bit definitions in SKCR
+ add keyboard controller registers
2002-12-18 04:09:31 +00:00
5abd84e433
Use callee-saved registers in RAS processing.
2002-12-17 20:49:07 +00:00
7443ad1b01
Move to MI runqueue functions.
2002-12-17 19:47:15 +00:00
5b6caeca74
Mark the Au1x00 CPUs as having a fully coherent data cache that doesn't
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require flushing (even in the instruction cache handlers). This gives
about a 4% improvement in a "make depend" benchmark.
Mark the SB-1 CPUs as having a fully coherent data cache that only
require flushing in the instruction cache handlers. This gives about
a 5% improvement in a "make depend" benchmark.
2002-12-17 12:07:50 +00:00
2c1a832f25
Add support for caches where the data cache is fully coherent, and
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either requires flushing either only when the I cache ops are used
or not at all. Currently only used by MIPS32/MIPS64 cache code.
2002-12-17 12:04:29 +00:00
a26cbfba69
Deal with an `unimplemented flush' trap from kernel mode.
2002-12-17 10:04:19 +00:00
30f7194bc4
use the __HAVE_CPU_MAXPROC hook to limit kern.maxproc to number
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of available GDT slots
add code in init386() to force maxproc to be maximum cpu_maxproc()
this fixes port-i386/1635 by John Kohl
2002-12-16 18:31:08 +00:00
c2ddc52f2d
The cache flush routines now take a CPU context parameter. This is going
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to be necessary in SMP kernels.
2002-12-16 16:59:09 +00:00
b036b089a7
Multiple inclusion protection.
2002-12-16 16:24:40 +00:00
4bd73a650e
Remove leftover declarations used for debugging purposes only.
2002-12-16 16:22:50 +00:00
0a3a2262cb
Increment version number for match function and Cycle 5 IP changes.
2002-12-16 13:02:58 +00:00
079b83cafa
Extend the matching routine to take a function pointer, so that additional
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(arbitrary) matching can be done.
Add match function and patch for Cycle 5 IP (Sparc 5 clone).
Reviewed by Uwe.
2002-12-16 13:01:01 +00:00
6ff0a8ba21
Initialize pools in pmap_init(); the low-water mark must be set when
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it is safe to allocate pages via the normal mechanism.
2002-12-16 07:18:30 +00:00
7affeb0071
Add support for RAS (initially added by me on nathanw_sa branch).
2002-12-16 02:15:58 +00:00
9ad045c958
Use MI setrunqueue()/remrunqueue().
2002-12-16 01:56:47 +00:00
ae7d5baab6
Fix pasto - make it compile for !MULTIPROCESSOR
2002-12-15 23:01:09 +00:00
9313f9570d
Disable `unimplemented flush' traps during boot. Keep it disabled on
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non-MULTIPROCESSOR kernels.
2002-12-15 15:01:08 +00:00
e9628b7102
Added Vrc4173PIU. (touch panel interface unit on Vrc4173)
2002-12-15 09:24:24 +00:00
cc079cff49
release the kernel lock if trace_enter fails.
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XXX[1]: We need to fix all platforms that do this.
XXX[2]: x86 does not check for MPSAFE syscalls before grabbing the lock.
2002-12-14 14:52:24 +00:00
b2622c34d6
In syscall_fancy(), drop the kernel lock if trace_enter fails.
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From Nick Hudson.
2002-12-14 14:40:36 +00:00
16c0ce8d78
Fix comment.
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De-__P().
2002-12-14 09:46:36 +00:00
058737862e
Now that gdt_compact() is gone, #if 0'ed gdt_shrink() doesn't need to be
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here, either. Remove other #if 0 code as well.
2002-12-14 09:38:50 +00:00
e0481a14c5
Change type of dumpmag from u_long to u_int32_t to sync with other ports.
2002-12-14 05:23:19 +00:00
0cc4fbf335
add twe control device
2002-12-13 23:26:47 +00:00
856e98cd30
bcopy -> memcpy, bzero -> memset
2002-12-13 20:44:44 +00:00
9ab86cb8ae
do a TBIAS after modifying cache enable bits
2002-12-13 18:52:56 +00:00
b36fe906bf
scatter some pmap_update(pmap_kernel()) to reduce differences to other ports
2002-12-13 18:50:22 +00:00
53cb6b767d
use <net/netisr_dispatch.h>
2002-12-13 18:49:35 +00:00
8cbcf0f7a3
Remove check for 32bit-only access of the old syscall path.
2002-12-13 17:44:13 +00:00
81a877b0f1
Restore all registers at sigreturn.
2002-12-13 02:52:10 +00:00
7f7f9da211
minor delint
2002-12-13 02:36:37 +00:00
ac22ef18d8
Remove redundant cli/sti instructions. From Enami Tsugutomo.
2002-12-12 21:39:33 +00:00
61b8a488ba
Add empty shells of new functions so we can keep compiling.
2002-12-12 17:42:10 +00:00
09e9a5cde9
This new file is wanted by compat_darwin.
2002-12-12 17:41:53 +00:00
c9498dd93c
add missing dependency.
2002-12-12 17:41:19 +00:00
91481144ea
Now that OpenBlockS code lives in evbppc, this directory is no longer needed.
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OK'd by masuda.
2002-12-12 13:54:43 +00:00
edba4e9dbc
Added some descriptions of OpenBlockS products just for your information.
2002-12-12 13:45:27 +00:00
8d55809f2f
Description file for OpenBlockS S and R.
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Those products are shipped from Plat'Home Inc.
See http://www.plathome.co.jp/
2002-12-12 12:51:37 +00:00
f4fe3fda21
dumpsys(): Use pmap_kremove() to unmap pages mapped pmap_kenter().
2002-12-12 09:34:04 +00:00
pk