pooka
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/* $NetBSD: macereg.h,v 1.2 2002/03/13 13:12:26 simonb Exp $ */
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/* $NetBSD: macereg.h,v 1.3 2002/12/23 20:05:06 pooka Exp $ */
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/*
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* Copyright (c) 2000 Soren S. Jorvang
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* XXX */
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#define MACE_BASE 0x1f000000
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#define MACE_PCI (MACE_BASE + 0x080000)
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#define MACE_PCI_ERROR_ADDR (MACE_PCI+0x0)
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#define MACE_PCI_ERROR_FLAGS (MACE_PCI+0x4)
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#define MACE_PCI_CONTROL (MACE_PCI+0x8)
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#define MACE_PCI_CONTROL_INT(x) BIT(x)
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#define MACE_PCI_CONTROL_INT_MASK 0xff
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#define MACE_PCI_CONTROL_SERR_ENA 0x0100
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#define MACE_PCI_CONTROL_ARB_N6 0x0200
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#define MACE_PCI_CONTROL_PARITY_ERR 0x0400
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#define MACE_PCI_CONTROL_MRMRA_ENA 0x0800
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#define MACE_PCI_CONTROL_ARB_N3 0x1000
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#define MACE_PCI_CONTROL_ARB_N4 0x2000
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#define MACE_PCI_CONTROL_ARB_N5 0x4000
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#define MACE_PCI_CONTROL_PARK_LIU 0x8000
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/* #define MACE_PCI_CONTROL_INV_INT(x) BIT(16+x)
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#define MACE_PCI_CONTROL_INV_INT_MASK 0x00ff0000
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#define MACE_PCI_CONTROL_OVERRUN_INT BIT(24)
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#define MACE_PCI_CONTROL_PARITY_INT BIT(25)
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#define MACE_PCI_CONTROL_SERR_INT BIT(26)
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#define MACE_PCI_CONTROL_IT_INT BIT(27)
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#define MACE_PCI_CONTROL_RE_INT BIT(28)
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#define MACE_PCI_CONTROL_DPED_INT BIT(29)
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#define MACE_PCI_CONTROL_TAR_INT BIT(30)
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#define MACE_PCI_CONTROL_MAR_INT BIT(31)
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*/
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#define MACE_PCI_REV_INFO_R (MACE_PCI+0xC)
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#define MACE_PCI_FLUSH_W (MACE_PCI+0xC)
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#define MACE_PCI_CONFIG_ADDR (MACE_PCI+0xCF4)
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#define MACE_PCI_CONFIG_DATA (MACE_PCI+0xCF8)
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#define MACE_PCI_LOW_MEMORY 0x1A000000
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#define MACE_PCI_LOW_IO 0x18000000
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#define MACE_PCI_NATIVE_VIEW 0x40000000
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#define MACE_PCI_IO 0x80000000
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#define MACE_PCI_HI_MEMORY 0x280000000
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#define MACE_PCI_HI_IO 0x100000000
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#define MACE_VIN1 (MACE_BASE + 0x100000)
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#define MACE_VIN2 (MACE_BASE + 0x180000)
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#define MACE_VOUT (MACE_BASE + 0x200000)
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#define MACE_ENET (MACE_BASE + 0x280000)
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#define MACE_PERIF (MACE_BASE + 0x300000)
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#define MACE_ISA_EXT (MACE_BASE + 0x380000)
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#define MACE_AUDIO (MACE_PERIF + 0x00000)
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#define MACE_ISA (MACE_PERIF + 0x10000)
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#define MACE_KBDMS (MACE_PERIF + 0x20000)
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#define MACE_I2C (MACE_PERIF + 0x30000)
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#define MACE_UST_MSC (MACE_PERIF + 0X40000)
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/***********************
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* PCI_ERROR_FLAGS Bits
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*/
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#define MACE_PERR_MASTER_ABORT 0x80000000
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#define MACE_PERR_TARGET_ABORT 0x40000000
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#define MACE_PERR_DATA_PARITY_ERR 0x20000000
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#define MACE_PERR_RETRY_ERR 0x10000000
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#define MACE_PERR_ILLEGAL_CMD 0x08000000
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#define MACE_PERR_SYSTEM_ERR 0x04000000
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#define MACE_PERR_INTERRUPT_TEST 0x02000000
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#define MACE_PERR_PARITY_ERR 0x01000000
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#define MACE_PERR_OVERRUN 0x00800000
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#define MACE_PERR_RSVD 0x00400000
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#define MACE_PERR_MEMORY_ADDR 0x00200000
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#define MACE_PERR_CONFIG_ADDR 0x00100000
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#define MACE_PERR_MASTER_ABORT_ADDR_VALID 0x00080000
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#define MACE_PERR_TARGET_ABORT_ADDR_VALID 0x00040000
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#define MACE_PERR_DATA_PARITY_ADDR_VALID 0x00020000
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#define MACE_PERR_RETRY_ADDR_VALID 0x00010000
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/*******************************
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* MACE ISA External Address Map
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*/
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#define MACE_ISA_EPP_BASE (MACE_ISA_EXT+0x00000)
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#define MACE_ISA_ECP_BASE (MACE_ISA_EXT+0x08000)
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#define MACE_ISA_SER1_BASE (MACE_ISA_EXT+0x10000)
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#define MACE_ISA_SER2_BASE (MACE_ISA_EXT+0x18000)
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#define MACE_ISA_RTC_BASE (MACE_ISA_EXT+0x20000)
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#define MACE_ISA_GAME_BASE (MACE_ISA_EXT_0x30000)
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/*************************
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* ISA Interface Registers
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*/
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/* ISA Ringbase Address and Reset Register */
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#define MACE_ISA_RINGBASE (MACE_ISA+0x0000)
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/* Flash-ROM/LED/DP-RAM/NIC Controller Register */
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#define MACE_ISA_FLASH_NIC_REG (MACE_ISA+0x0008)
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#define MACE_ISA_FLASH_WE (0x01) /* 1=> Enable FLASH writes */
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#define MACE_ISA_PWD_CLEAR (0x02) /* 1=> PWD CLEAR jumper detected */
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#define MACE_ISA_NIC_DEASSERT (0x04)
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#define MACE_ISA_NIC_DATA (0x08)
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#define MACE_ISA_LED_RED (0x10) /* 1=> Illuminate RED LED */
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#define MACE_ISA_LED_GREEN (0x20) /* 1=> Illuminate GREEN LED */
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#define MACE_ISA_DP_RAM_ENABLE (0x40)
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/* Interrupt Status and Mask Registers (32 bits) */
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#define MACE_ISA_INT_STATUS (MACE_ISA+0x0010)
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#define MACE_ISA_INT_MASK (MACE_ISA+0x0018)
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/* bit definitions */
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#define MACE_ISA_INT_RTC_IRQ (0x00000100)
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/********************************
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* MACE Timer Interface Registers
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*
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* Note: MSC_UST<31:0> is MSC, MSC_UST<63:32> is UST.
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*/
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#define MACE_UST (MACE_UST_MSC + 0x00) /* Universial system time */
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#define MACE_COMPARE1 (MACE_UST_MSC + 0x08) /* Interrupt compare reg 1 */
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#define MACE_COMPARE2 (MACE_UST_MSC + 0x10) /* Interrupt compare reg 2 */
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#define MACE_COMPARE3 (MACE_UST_MSC + 0x18) /* Interrupt compare reg 3 */
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#define MACE_UST_PERIOD 960 /* UST Period in ns */
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#define MACE_AIN_MSC_UST (MACE_UST_MSC + 0x20) /* Audio in MSC/UST pair */
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#define MACE_AOUT1_MSC_UST (MACE_UST_MSC + 0x28) /* Audio out 1 MSC/UST pair */
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#define MACE_AOUT2_MSC_UST (MACE_UST_MSC + 0x30) /* Audio out 2 MSC/UST pair */
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#define MACE_VIN1_MSC_UST (MACE_UST_MSC + 0x38) /* Video In 1 MSC/UST pair */
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#define MACE_VIN2_MSC_UST (MACE_UST_MSC + 0x40) /* Video In 2 MSC/UST pair */
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#define MACE_VOUT_MSC_UST (MACE_UST_MSC + 0x48) /* Video out MSC/UST pair */
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