From 0dd7013e7a7eb5b7dd1f7fd300c8c4ce4bc77cb5 Mon Sep 17 00:00:00 2001 From: pooka Date: Mon, 23 Dec 2002 20:05:06 +0000 Subject: [PATCH] MACE register definitions from Chris Sekiya --- sys/arch/sgimips/dev/macereg.h | 139 ++++++++++++++++++++++++++++++++- 1 file changed, 137 insertions(+), 2 deletions(-) diff --git a/sys/arch/sgimips/dev/macereg.h b/sys/arch/sgimips/dev/macereg.h index 01894cea5657..8ea2428e0680 100644 --- a/sys/arch/sgimips/dev/macereg.h +++ b/sys/arch/sgimips/dev/macereg.h @@ -1,4 +1,4 @@ -/* $NetBSD: macereg.h,v 1.2 2002/03/13 13:12:26 simonb Exp $ */ +/* $NetBSD: macereg.h,v 1.3 2002/12/23 20:05:06 pooka Exp $ */ /* * Copyright (c) 2000 Soren S. Jorvang @@ -32,4 +32,139 @@ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* XXX */ +#define MACE_BASE 0x1f000000 + +#define MACE_PCI (MACE_BASE + 0x080000) +#define MACE_PCI_ERROR_ADDR (MACE_PCI+0x0) +#define MACE_PCI_ERROR_FLAGS (MACE_PCI+0x4) + +#define MACE_PCI_CONTROL (MACE_PCI+0x8) +#define MACE_PCI_CONTROL_INT(x) BIT(x) +#define MACE_PCI_CONTROL_INT_MASK 0xff +#define MACE_PCI_CONTROL_SERR_ENA 0x0100 +#define MACE_PCI_CONTROL_ARB_N6 0x0200 +#define MACE_PCI_CONTROL_PARITY_ERR 0x0400 +#define MACE_PCI_CONTROL_MRMRA_ENA 0x0800 +#define MACE_PCI_CONTROL_ARB_N3 0x1000 +#define MACE_PCI_CONTROL_ARB_N4 0x2000 +#define MACE_PCI_CONTROL_ARB_N5 0x4000 +#define MACE_PCI_CONTROL_PARK_LIU 0x8000 + +/* #define MACE_PCI_CONTROL_INV_INT(x) BIT(16+x) +#define MACE_PCI_CONTROL_INV_INT_MASK 0x00ff0000 +#define MACE_PCI_CONTROL_OVERRUN_INT BIT(24) +#define MACE_PCI_CONTROL_PARITY_INT BIT(25) +#define MACE_PCI_CONTROL_SERR_INT BIT(26) +#define MACE_PCI_CONTROL_IT_INT BIT(27) +#define MACE_PCI_CONTROL_RE_INT BIT(28) +#define MACE_PCI_CONTROL_DPED_INT BIT(29) +#define MACE_PCI_CONTROL_TAR_INT BIT(30) +#define MACE_PCI_CONTROL_MAR_INT BIT(31) +*/ + + +#define MACE_PCI_REV_INFO_R (MACE_PCI+0xC) +#define MACE_PCI_FLUSH_W (MACE_PCI+0xC) +#define MACE_PCI_CONFIG_ADDR (MACE_PCI+0xCF4) +#define MACE_PCI_CONFIG_DATA (MACE_PCI+0xCF8) +#define MACE_PCI_LOW_MEMORY 0x1A000000 +#define MACE_PCI_LOW_IO 0x18000000 +#define MACE_PCI_NATIVE_VIEW 0x40000000 +#define MACE_PCI_IO 0x80000000 +#define MACE_PCI_HI_MEMORY 0x280000000 +#define MACE_PCI_HI_IO 0x100000000 + + + +#define MACE_VIN1 (MACE_BASE + 0x100000) +#define MACE_VIN2 (MACE_BASE + 0x180000) +#define MACE_VOUT (MACE_BASE + 0x200000) +#define MACE_ENET (MACE_BASE + 0x280000) +#define MACE_PERIF (MACE_BASE + 0x300000) +#define MACE_ISA_EXT (MACE_BASE + 0x380000) + +#define MACE_AUDIO (MACE_PERIF + 0x00000) +#define MACE_ISA (MACE_PERIF + 0x10000) +#define MACE_KBDMS (MACE_PERIF + 0x20000) +#define MACE_I2C (MACE_PERIF + 0x30000) +#define MACE_UST_MSC (MACE_PERIF + 0X40000) + + + +/*********************** + * PCI_ERROR_FLAGS Bits + */ +#define MACE_PERR_MASTER_ABORT 0x80000000 +#define MACE_PERR_TARGET_ABORT 0x40000000 +#define MACE_PERR_DATA_PARITY_ERR 0x20000000 +#define MACE_PERR_RETRY_ERR 0x10000000 +#define MACE_PERR_ILLEGAL_CMD 0x08000000 +#define MACE_PERR_SYSTEM_ERR 0x04000000 +#define MACE_PERR_INTERRUPT_TEST 0x02000000 +#define MACE_PERR_PARITY_ERR 0x01000000 +#define MACE_PERR_OVERRUN 0x00800000 +#define MACE_PERR_RSVD 0x00400000 +#define MACE_PERR_MEMORY_ADDR 0x00200000 +#define MACE_PERR_CONFIG_ADDR 0x00100000 +#define MACE_PERR_MASTER_ABORT_ADDR_VALID 0x00080000 +#define MACE_PERR_TARGET_ABORT_ADDR_VALID 0x00040000 +#define MACE_PERR_DATA_PARITY_ADDR_VALID 0x00020000 +#define MACE_PERR_RETRY_ADDR_VALID 0x00010000 + + +/******************************* + * MACE ISA External Address Map + */ +#define MACE_ISA_EPP_BASE (MACE_ISA_EXT+0x00000) +#define MACE_ISA_ECP_BASE (MACE_ISA_EXT+0x08000) +#define MACE_ISA_SER1_BASE (MACE_ISA_EXT+0x10000) +#define MACE_ISA_SER2_BASE (MACE_ISA_EXT+0x18000) +#define MACE_ISA_RTC_BASE (MACE_ISA_EXT+0x20000) +#define MACE_ISA_GAME_BASE (MACE_ISA_EXT_0x30000) + + +/************************* + * ISA Interface Registers + */ + +/* ISA Ringbase Address and Reset Register */ + +#define MACE_ISA_RINGBASE (MACE_ISA+0x0000) + +/* Flash-ROM/LED/DP-RAM/NIC Controller Register */ + +#define MACE_ISA_FLASH_NIC_REG (MACE_ISA+0x0008) +#define MACE_ISA_FLASH_WE (0x01) /* 1=> Enable FLASH writes */ +#define MACE_ISA_PWD_CLEAR (0x02) /* 1=> PWD CLEAR jumper detected */ +#define MACE_ISA_NIC_DEASSERT (0x04) +#define MACE_ISA_NIC_DATA (0x08) +#define MACE_ISA_LED_RED (0x10) /* 1=> Illuminate RED LED */ +#define MACE_ISA_LED_GREEN (0x20) /* 1=> Illuminate GREEN LED */ +#define MACE_ISA_DP_RAM_ENABLE (0x40) + +/* Interrupt Status and Mask Registers (32 bits) */ + +#define MACE_ISA_INT_STATUS (MACE_ISA+0x0010) +#define MACE_ISA_INT_MASK (MACE_ISA+0x0018) + +/* bit definitions */ +#define MACE_ISA_INT_RTC_IRQ (0x00000100) + + +/******************************** + * MACE Timer Interface Registers + * + * Note: MSC_UST<31:0> is MSC, MSC_UST<63:32> is UST. + */ +#define MACE_UST (MACE_UST_MSC + 0x00) /* Universial system time */ +#define MACE_COMPARE1 (MACE_UST_MSC + 0x08) /* Interrupt compare reg 1 */ +#define MACE_COMPARE2 (MACE_UST_MSC + 0x10) /* Interrupt compare reg 2 */ +#define MACE_COMPARE3 (MACE_UST_MSC + 0x18) /* Interrupt compare reg 3 */ +#define MACE_UST_PERIOD 960 /* UST Period in ns */ + +#define MACE_AIN_MSC_UST (MACE_UST_MSC + 0x20) /* Audio in MSC/UST pair */ +#define MACE_AOUT1_MSC_UST (MACE_UST_MSC + 0x28) /* Audio out 1 MSC/UST pair */ +#define MACE_AOUT2_MSC_UST (MACE_UST_MSC + 0x30) /* Audio out 2 MSC/UST pair */ +#define MACE_VIN1_MSC_UST (MACE_UST_MSC + 0x38) /* Video In 1 MSC/UST pair */ +#define MACE_VIN2_MSC_UST (MACE_UST_MSC + 0x40) /* Video In 2 MSC/UST pair */ +#define MACE_VOUT_MSC_UST (MACE_UST_MSC + 0x48) /* Video out MSC/UST pair */