* map the PROM CPU mailbox if available.
* map MXCC error/status registers if available. * add MXCC-specific module error interrupt handler. * use high priority interrupt level in mp_pause_cpus()
This commit is contained in:
pk
parent
2b59d26892
commit
83dae8a821
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu.c,v 1.144 2002/12/28 02:35:56 mrg Exp $ */
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/* $NetBSD: cpu.c,v 1.145 2002/12/31 15:10:28 pk Exp $ */
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/*
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* Copyright (c) 1996
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@ -226,8 +226,13 @@ alloc_cpuinfo()
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pmap_update(pmap_kernel());
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bzero((void *)cpi, sz);
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#if 0
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cpi->eintstack = (void *)((vaddr_t)cpi + sz);
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cpi->idle_u = (void *)((vaddr_t)cpi + sz - INT_STACK_SIZE - USPACE);
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#else
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cpi->eintstack = (void *)((vaddr_t)cpi + sz - USPACE);
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cpi->idle_u = (void *)((vaddr_t)cpi + sz - USPACE);
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#endif
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return (cpi);
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}
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@ -290,10 +295,64 @@ cpu_mainbus_attach(parent, self, aux)
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void *aux;
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{
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struct mainbus_attach_args *ma = aux;
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int mid;
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struct openprom_addr *rrp = NULL;
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struct cpu_info *cpi;
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int mid, node;
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int error, n;
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mid = (ma->ma_node != 0) ? PROM_getpropint(ma->ma_node, "mid", 0) : 0;
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cpu_attach((struct cpu_softc *)self, ma->ma_node, mid);
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node = ma->ma_node;
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mid = (node != 0) ? PROM_getpropint(node, "mid", 0) : 0;
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cpu_attach((struct cpu_softc *)self, node, mid);
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cpi = ((struct cpu_softc *)self)->sc_cpuinfo;
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/*
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* Map CPU mailbox if available
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*/
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if (node != 0 && (error = PROM_getprop(node, "mailbox",
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sizeof(struct openprom_addr),
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&n, (void **)&rrp)) == 0) {
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if (bus_space_map(ma->ma_bustag,
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BUS_ADDR(rrp[0].oa_space, rrp[0].oa_base),
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rrp[0].oa_size,
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BUS_SPACE_MAP_LINEAR,
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&cpi->mailbox) != 0)
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panic("%s: can't map cpu mailbox", self->dv_xname);
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free(rrp, M_DEVBUF);
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}
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/*
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* Map Module Control Space if available
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*/
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if (cpi->mxcc == 0)
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/* We only know what it means on MXCCs */
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return;
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rrp = NULL;
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if (node == 0 || (error = PROM_getprop(node, "reg",
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sizeof(struct openprom_addr),
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&n, (void **)&rrp)) != 0)
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return;
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/* register set #0 is the MBus port register */
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if (bus_space_map(ma->ma_bustag,
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BUS_ADDR(rrp[0].oa_space, rrp[0].oa_base),
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rrp[0].oa_size,
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BUS_SPACE_MAP_LINEAR,
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&cpi->ci_mbusport) != 0) {
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panic("%s: can't map cpu regs", self->dv_xname);
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}
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/* register set #1: MCXX control */
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if (bus_space_map(ma->ma_bustag,
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BUS_ADDR(rrp[1].oa_space, rrp[1].oa_base),
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rrp[1].oa_size,
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BUS_SPACE_MAP_LINEAR,
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&cpi->ci_mxccregs) != 0) {
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panic("%s: can't map cpu regs", self->dv_xname);
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}
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/* register sets #3 and #4 are E$ cache data and tags */
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free(rrp, M_DEVBUF);
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}
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#if defined(SUN4D)
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@ -612,8 +671,7 @@ xcall(func, arg0, arg1, arg2, arg3, cpuset)
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p->arg1 = arg1;
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p->arg2 = arg2;
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p->arg3 = arg3;
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cpi->intreg_4m->pi_set = PINTR_SINTRLEV(13);/*xcall_cookie->pil*/
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/*was: raise_ipi(cpi);*/
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raise_ipi(cpi,13);/*xcall_cookie->pil*/
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}
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/*
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@ -682,10 +740,9 @@ mp_pause_cpus()
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if (CPU_NOTREADY(cpi))
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continue;
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simple_lock(&cpi->msg.lock);
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cpi->msg.tag = XPMSG_PAUSECPU;
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cpi->flags &= ~CPUFLG_GOTMSG;
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cpi->intreg_4m->pi_set = PINTR_SINTRLEV(13);/*xcall_cookie->pil*/
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raise_ipi(cpi,15); /* high priority intr */
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}
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UNLOCK_XPMSG();
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}
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@ -838,6 +895,9 @@ int hypersparc_get_asyncflt __P((u_int *, u_int *));
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int cypress_get_asyncflt __P((u_int *, u_int *));
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int no_asyncflt_regs __P((u_int *, u_int *));
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int (*moduleerr_handler) __P((void));
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int viking_module_error(void);
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struct module_info module_unknown = {
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CPUTYP_UNKNOWN,
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VAC_UNKNOWN,
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@ -1514,6 +1574,8 @@ viking_hotfix(sc)
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sc->flags |= CPUFLG_CACHE_MANDATORY;
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sc->zero_page = pmap_zero_page_viking_mxcc;
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sc->copy_page = pmap_copy_page_viking_mxcc;
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moduleerr_handler = viking_module_error;
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/*
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* Ok to cache PTEs; set the flag here, so we don't
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* uncache in pmap_bootstrap().
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@ -1550,6 +1612,37 @@ viking_mmu_enable()
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pcr &= ~VIKING_PCR_TC;
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sta(SRMMU_PCR, ASI_SRMMU, pcr);
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}
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int
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viking_module_error(void)
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{
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u_int64_t v;
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int n, fatal = 0;
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/* Report on MXCC error registers in each module */
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for (n = 0; n < ncpu; n++) {
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struct cpu_info *cpi = cpus[n];
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if (cpi->ci_mxccregs == 0) {
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printf("\tMXCC registers not mapped\n");
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continue;
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}
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printf("module%d:\n", cpi->ci_cpuid);
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v = *((u_int64_t *)(cpi->ci_mxccregs + 0xe00));
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printf("\tmxcc error 0x%llx\n", v);
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v = *((u_int64_t *)(cpi->ci_mxccregs + 0xb00));
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printf("\tmxcc status 0x%llx\n", v);
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v = *((u_int64_t *)(cpi->ci_mxccregs + 0xc00));
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printf("\tmxcc reset 0x%llx", v);
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if (v & MXCC_MRST_WD)
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printf(" (WATCHDOG RESET)"), fatal = 1;
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if (v & MXCC_MRST_SI)
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printf(" (SOFTWARE RESET)"), fatal = 1;
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printf("\n");
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}
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return (fatal);
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}
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#endif /* SUN4M || SUN4D */
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#if defined(SUN4D)
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@ -1,4 +1,4 @@
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/* $NetBSD: intr.c,v 1.69 2002/12/23 00:55:18 pk Exp $ */
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/* $NetBSD: intr.c,v 1.70 2002/12/31 15:10:28 pk Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -168,6 +168,7 @@ int (*moduleerr_handler) __P((void));
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#if defined(MULTIPROCESSOR)
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volatile int nmi_hard_wait = 0;
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struct simplelock nmihard_lock = SIMPLELOCK_INITIALIZER;
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int drop_into_rom_on_fatal = 1;
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#endif
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void
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@ -204,11 +205,15 @@ nmi_hard()
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;
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return;
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} else {
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int n = 0;
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int n = 100000;
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while (nmi_hard_wait < ncpu)
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if (n++ > 100000)
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panic("nmi_hard: SMP botch.");
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while (nmi_hard_wait < ncpu) {
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DELAY(1);
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if (n-- > 0)
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continue;
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printf("nmi_hard: SMP botch.");
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break;
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}
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}
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#endif
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simple_lock(&nmihard_lock);
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nmi_hard_wait = 0;
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simple_unlock(&nmihard_lock);
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if (fatal && drop_into_rom_on_fatal) {
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callrom();
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return;
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}
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#endif
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if (fatal)
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@ -262,7 +271,7 @@ nmi_soft(tf)
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{
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/* XXX - Most of this is superseded by xcallintr() below */
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#ifdef MULTIPROCESSOR
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#if defined(MULTIPROCESSOR)
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switch (cpuinfo.msg.tag) {
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case XPMSG_SAVEFPU:
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savefpstate(cpuinfo.fpproc->p_md.md_fpstate);
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@ -286,6 +295,7 @@ nmi_soft(tf)
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break;
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}
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}
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cpuinfo.msg.tag = 0;
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cpuinfo.flags |= CPUFLG_GOTMSG;
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#endif
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}
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break;
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}
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}
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cpuinfo.msg.tag = 0;
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cpuinfo.flags |= CPUFLG_GOTMSG;
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}
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#endif /* MULTIPROCESSOR */
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