Brush-up the generic cross-call routine and use it to implement the SMP
cache flush ops. Also a standard soft interrupt handler for standard cross-call notification reserving the NMI level 15 softint for urgent cross calls.
This commit is contained in:
pk
parent
eaf530d598
commit
75c5f270d2
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@ -1,4 +1,4 @@
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/* $NetBSD: cache.c,v 1.66 2002/12/16 16:59:10 pk Exp $ */
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/* $NetBSD: cache.c,v 1.67 2002/12/19 10:38:28 pk Exp $ */
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/*
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* Copyright (c) 1996
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@ -280,7 +280,7 @@ cypress_cache_enable()
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cache_alias_bits = (cache_alias_dist - 1) & ~PGOFSET;
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pcr = lda(SRMMU_PCR, ASI_SRMMU);
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pcr &= ~(CYPRESS_PCR_CE | CYPRESS_PCR_CM);
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pcr &= ~CYPRESS_PCR_CM;
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/* Now reset cache tag memory if cache not yet enabled */
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ls = CACHEINFO.c_linesize;
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@ -974,28 +974,7 @@ smp_vcache_flush_page(va, ctx)
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int va;
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int ctx;
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{
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int n, s;
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cpuinfo.sp_vcache_flush_page(va, ctx);
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if (cold || (cpuinfo.flags & CPUFLG_READY) == 0)
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return;
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LOCK_XPMSG();
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for (n = 0; n < ncpu; n++) {
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struct cpu_info *cpi = cpus[n];
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struct xpmsg_flush_page *p;
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if (CPU_READY(cpi))
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continue;
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p = &cpi->msg.u.xpmsg_flush_page;
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s = splhigh();
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simple_lock(&cpi->msg.lock);
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cpi->msg.tag = XPMSG_VCACHE_FLUSH_PAGE;
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p->ctx = getcontext4m();
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p->va = va;
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raise_ipi_wait_and_unlock(cpi);
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splx(s);
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}
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UNLOCK_XPMSG();
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xcall((xcall_func_t)cpuinfo.sp_vcache_flush_page, va, ctx, 0, 0, 0);
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}
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void
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@ -1003,29 +982,7 @@ smp_vcache_flush_segment(vr, vs, ctx)
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int vr, vs;
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int ctx;
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{
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int n, s;
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cpuinfo.sp_vcache_flush_segment(vr, vs, ctx);
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if (cold || (cpuinfo.flags & CPUFLG_READY) == 0)
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return;
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LOCK_XPMSG();
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for (n = 0; n < ncpu; n++) {
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struct cpu_info *cpi = cpus[n];
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struct xpmsg_flush_segment *p;
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if (CPU_READY(cpi))
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continue;
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p = &cpi->msg.u.xpmsg_flush_segment;
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s = splhigh();
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simple_lock(&cpi->msg.lock);
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cpi->msg.tag = XPMSG_VCACHE_FLUSH_SEGMENT;
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p->ctx = getcontext4m();
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p->vr = vr;
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p->vs = vs;
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raise_ipi_wait_and_unlock(cpi);
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splx(s);
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}
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UNLOCK_XPMSG();
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xcall((xcall_func_t)cpuinfo.sp_vcache_flush_segment, vr, vs, ctx, 0, 0);
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}
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void
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@ -1033,84 +990,22 @@ smp_vcache_flush_region(vr, ctx)
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int vr;
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int ctx;
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{
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int n, s;
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cpuinfo.sp_vcache_flush_region(vr, ctx);
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if (cold || (cpuinfo.flags & CPUFLG_READY) == 0)
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return;
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LOCK_XPMSG();
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for (n = 0; n < ncpu; n++) {
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struct cpu_info *cpi = cpus[n];
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struct xpmsg_flush_region *p;
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if (CPU_READY(cpi))
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continue;
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p = &cpi->msg.u.xpmsg_flush_region;
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s = splhigh();
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simple_lock(&cpi->msg.lock);
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cpi->msg.tag = XPMSG_VCACHE_FLUSH_REGION;
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p->ctx = getcontext4m();
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p->vr = vr;
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raise_ipi_wait_and_unlock(cpi);
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splx(s);
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}
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UNLOCK_XPMSG();
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xcall((xcall_func_t)cpuinfo.sp_vcache_flush_region, vr, ctx, 0, 0, 0);
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}
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void
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smp_vcache_flush_context(ctx)
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int ctx;
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{
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int n, s;
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cpuinfo.sp_vcache_flush_context(ctx);
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if (cold || (cpuinfo.flags & CPUFLG_READY) == 0)
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return;
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LOCK_XPMSG();
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for (n = 0; n < ncpu; n++) {
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struct cpu_info *cpi = cpus[n];
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struct xpmsg_flush_context *p;
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if (CPU_READY(cpi))
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continue;
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p = &cpi->msg.u.xpmsg_flush_context;
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s = splhigh();
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simple_lock(&cpi->msg.lock);
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cpi->msg.tag = XPMSG_VCACHE_FLUSH_CONTEXT;
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p->ctx = ctx;
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raise_ipi_wait_and_unlock(cpi);
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splx(s);
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}
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UNLOCK_XPMSG();
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xcall((xcall_func_t)cpuinfo.sp_vcache_flush_context, ctx, 0, 0, 0, 0);
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}
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void
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smp_cache_flush(va, size)
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smp_cache_flush(va, size, ctx)
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caddr_t va;
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u_int size;
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int ctx;
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{
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int n, s;
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cpuinfo.sp_cache_flush(va, size);
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if (cold || (cpuinfo.flags & CPUFLG_READY) == 0)
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return;
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LOCK_XPMSG();
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for (n = 0; n < ncpu; n++) {
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struct cpu_info *cpi = cpus[n];
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struct xpmsg_flush_range *p;
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if (CPU_READY(cpi))
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continue;
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p = &cpi->msg.u.xpmsg_flush_range;
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s = splhigh();
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simple_lock(&cpi->msg.lock);
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cpi->msg.tag = XPMSG_VCACHE_FLUSH_RANGE;
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p->ctx = getcontext4m();
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p->va = va;
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p->size = size;
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raise_ipi_wait_and_unlock(cpi);
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splx(s);
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}
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UNLOCK_XPMSG();
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xcall((xcall_func_t)cpuinfo.sp_cache_flush, (int)va, (int)size, ctx, 0, 0);
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}
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#endif /* MULTIPROCESSOR */
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu.c,v 1.139 2002/12/16 16:59:10 pk Exp $ */
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/* $NetBSD: cpu.c,v 1.140 2002/12/19 10:38:28 pk Exp $ */
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/*
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* Copyright (c) 1996
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@ -75,6 +75,10 @@
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#include <machine/oldmon.h>
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#include <machine/idprom.h>
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#if defined(MULTIPROCESSOR) && defined(DDB)
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#include <machine/db_machdep.h>
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#endif
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#include <sparc/sparc/cache.h>
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#include <sparc/sparc/asm.h>
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#include <sparc/sparc/cpuvar.h>
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@ -554,55 +558,34 @@ extern void cpu_hatch __P((void)); /* in locore.s */
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printf("CPU did not spin up\n");
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}
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/*
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* Calls raise_ipi(), waits for the remote CPU to notice the message, and
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* unlocks this CPU's message lock, which we expect was locked at entry.
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*/
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void
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raise_ipi_wait_and_unlock(cpi)
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struct cpu_info *cpi;
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{
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int i;
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raise_ipi(cpi);
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i = 0;
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while ((cpi->flags & CPUFLG_GOTMSG) == 0) {
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if (i++ > 500000) {
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printf("raise_ipi_wait_and_unlock(cpu%d): couldn't ping cpu%d\n",
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cpuinfo.ci_cpuid, cpi->ci_cpuid);
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break;
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}
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}
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simple_unlock(&cpi->msg.lock);
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}
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/*
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* Call a function on every CPU. One must hold xpmsg_lock around
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* this function.
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*/
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void
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cross_call(func, arg0, arg1, arg2, arg3, cpuset)
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xcall(func, arg0, arg1, arg2, arg3, cpuset)
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int (*func)(int, int, int, int);
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int arg0, arg1, arg2, arg3;
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int cpuset; /* XXX unused; cpus to send to: we do all */
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{
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int n, i, not_done;
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struct xpmsg_func *p;
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int s, n, i, done;
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volatile struct xpmsg_func *p;
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/* XXX - note p->retval is probably no longer useful */
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/*
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* If no cpus are configured yet, just call ourselves.
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*/
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if (cpus == NULL) {
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p = &cpuinfo.msg.u.xpmsg_func;
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p->func = func;
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p->arg0 = arg0;
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p->arg1 = arg1;
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p->arg2 = arg2;
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p->arg3 = arg3;
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p->retval = (*p->func)(p->arg0, p->arg1, p->arg2, p->arg3);
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if (func)
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p->retval = (*func)(arg0, arg1, arg2, arg3);
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return;
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}
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s = splvm(); /* XXX - should validate this level */
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LOCK_XPMSG();
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/*
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* Firstly, call each CPU. We do this so that they might have
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* finished by the time we start looking.
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@ -615,55 +598,47 @@ cross_call(func, arg0, arg1, arg2, arg3, cpuset)
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simple_lock(&cpi->msg.lock);
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cpi->msg.tag = XPMSG_FUNC;
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cpi->flags &= ~CPUFLG_GOTMSG;
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p = &cpi->msg.u.xpmsg_func;
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p->func = func;
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p->arg0 = arg0;
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p->arg1 = arg1;
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p->arg2 = arg2;
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p->arg3 = arg3;
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cpi->flags &= ~CPUFLG_GOTMSG;
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raise_ipi(cpi);
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cpi->intreg_4m->pi_set = PINTR_SINTRLEV(13);/*xcall_cookie->pil*/
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/*was: raise_ipi(cpi);*/
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}
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/*
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* Second, call ourselves.
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*/
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p = &cpuinfo.msg.u.xpmsg_func;
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/* Call this on me first. */
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p->func = func;
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p->arg0 = arg0;
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p->arg1 = arg1;
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p->arg2 = arg2;
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p->arg3 = arg3;
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p->retval = (*p->func)(p->arg0, p->arg1, p->arg2, p->arg3);
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if (func)
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p->retval = (*func)(arg0, arg1, arg2, arg3);
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/*
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* Lastly, start looping, waiting for all cpu's to register that they
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* have completed (bailing if it takes "too long", being loud about
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* this in the process).
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*/
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i = 0;
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while (not_done) {
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not_done = 0;
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done = 0;
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i = 100000; /* time-out */
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while (!done) {
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done = 1;
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for (n = 0; n < ncpu; n++) {
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struct cpu_info *cpi = cpus[n];
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if (CPU_READY(cpi))
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continue;
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if ((cpi->flags & CPUFLG_GOTMSG) != 0)
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not_done = 1;
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if ((cpi->flags & CPUFLG_GOTMSG) == 0)
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done = 0;
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}
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if (not_done && i++ > 100000) {
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printf("cross_call(cpu%d): couldn't ping cpus:",
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cpuinfo.ci_cpuid);
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if (!done && i-- < 0) {
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printf("xcall(cpu%d,%p): couldn't ping cpus:",
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cpuinfo.ci_cpuid, func);
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break;
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}
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if (not_done == 0)
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break;
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}
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for (n = 0; n < ncpu; n++) {
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struct cpu_info *cpi = cpus[n];
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@ -671,11 +646,14 @@ cross_call(func, arg0, arg1, arg2, arg3, cpuset)
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if (CPU_READY(cpi))
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continue;
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simple_unlock(&cpi->msg.lock);
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if ((cpi->flags & CPUFLG_GOTMSG) != 0)
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if ((cpi->flags & CPUFLG_GOTMSG) == 0)
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printf(" cpu%d", cpi->ci_cpuid);
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}
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if (not_done)
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if (!done)
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printf("\n");
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UNLOCK_XPMSG();
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splx(s);
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}
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void
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@ -686,6 +664,7 @@ mp_pause_cpus()
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if (cpus == NULL)
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return;
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/* XXX - can currently be called at a high IPL level */
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LOCK_XPMSG();
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for (n = 0; n < ncpu; n++) {
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struct cpu_info *cpi = cpus[n];
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@ -696,7 +675,7 @@ mp_pause_cpus()
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simple_lock(&cpi->msg.lock);
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cpi->msg.tag = XPMSG_PAUSECPU;
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cpi->flags &= ~CPUFLG_GOTMSG;
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raise_ipi_wait_and_unlock(cpi);
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cpi->intreg_4m->pi_set = PINTR_SINTRLEV(13);/*xcall_cookie->pil*/
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}
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UNLOCK_XPMSG();
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: intr.c,v 1.66 2002/12/18 06:20:36 mrg Exp $ */
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/* $NetBSD: intr.c,v 1.67 2002/12/19 10:38:28 pk Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -73,6 +73,9 @@
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#endif
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void *softnet_cookie;
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#if defined(MULTIPROCESSOR)
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void *xcall_cookie;
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#endif
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void strayintr __P((struct clockframe *));
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#ifdef DIAGNOSTIC
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@ -250,11 +253,15 @@ nmi_hard()
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panic("nmi");
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}
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/*
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* Non-maskable soft interrupt level 15 handler
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*/
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void
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nmi_soft(tf)
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struct trapframe *tf;
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{
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/* XXX - Most of this is superseded by xcallintr() below */
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#ifdef MULTIPROCESSOR
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switch (cpuinfo.msg.tag) {
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case XPMSG_SAVEFPU:
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@ -282,14 +289,14 @@ nmi_soft(tf)
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}
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case XPMSG_FUNC:
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{
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struct xpmsg_func *p = &cpuinfo.msg.u.xpmsg_func;
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volatile struct xpmsg_func *p = &cpuinfo.msg.u.xpmsg_func;
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p->retval = (*p->func)(p->arg0, p->arg1, p->arg2, p->arg3);
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break;
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}
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case XPMSG_VCACHE_FLUSH_PAGE:
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{
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struct xpmsg_flush_page *p = &cpuinfo.msg.u.xpmsg_flush_page;
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volatile struct xpmsg_flush_page *p = &cpuinfo.msg.u.xpmsg_flush_page;
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int ctx = getcontext();
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setcontext(p->ctx);
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@ -299,7 +306,7 @@ nmi_soft(tf)
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}
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case XPMSG_VCACHE_FLUSH_SEGMENT:
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{
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struct xpmsg_flush_segment *p = &cpuinfo.msg.u.xpmsg_flush_segment;
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volatile struct xpmsg_flush_segment *p = &cpuinfo.msg.u.xpmsg_flush_segment;
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int ctx = getcontext();
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setcontext(p->ctx);
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@ -309,7 +316,7 @@ nmi_soft(tf)
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}
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case XPMSG_VCACHE_FLUSH_REGION:
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{
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struct xpmsg_flush_region *p = &cpuinfo.msg.u.xpmsg_flush_region;
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volatile struct xpmsg_flush_region *p = &cpuinfo.msg.u.xpmsg_flush_region;
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int ctx = getcontext();
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setcontext(p->ctx);
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@ -319,7 +326,7 @@ nmi_soft(tf)
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}
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case XPMSG_VCACHE_FLUSH_CONTEXT:
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{
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struct xpmsg_flush_context *p = &cpuinfo.msg.u.xpmsg_flush_context;
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volatile struct xpmsg_flush_context *p = &cpuinfo.msg.u.xpmsg_flush_context;
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int ctx = getcontext();
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setcontext(p->ctx);
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@ -329,17 +336,17 @@ nmi_soft(tf)
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}
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case XPMSG_VCACHE_FLUSH_RANGE:
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{
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struct xpmsg_flush_range *p = &cpuinfo.msg.u.xpmsg_flush_range;
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volatile struct xpmsg_flush_range *p = &cpuinfo.msg.u.xpmsg_flush_range;
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int ctx = getcontext();
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setcontext(p->ctx);
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cpuinfo.sp_cache_flush(p->va, p->size);
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cpuinfo.sp_cache_flush(p->va, p->size, p->ctx);
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setcontext(ctx);
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break;
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}
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case XPMSG_DEMAP_TLB_PAGE:
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{
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struct xpmsg_flush_page *p = &cpuinfo.msg.u.xpmsg_flush_page;
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volatile struct xpmsg_flush_page *p = &cpuinfo.msg.u.xpmsg_flush_page;
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int ctx = getcontext();
|
||||
|
||||
setcontext(p->ctx);
|
||||
|
|
@ -349,7 +356,7 @@ nmi_soft(tf)
|
|||
}
|
||||
case XPMSG_DEMAP_TLB_SEGMENT:
|
||||
{
|
||||
struct xpmsg_flush_segment *p = &cpuinfo.msg.u.xpmsg_flush_segment;
|
||||
volatile struct xpmsg_flush_segment *p = &cpuinfo.msg.u.xpmsg_flush_segment;
|
||||
int ctx = getcontext();
|
||||
|
||||
setcontext(p->ctx);
|
||||
|
|
@ -359,7 +366,7 @@ nmi_soft(tf)
|
|||
}
|
||||
case XPMSG_DEMAP_TLB_REGION:
|
||||
{
|
||||
struct xpmsg_flush_region *p = &cpuinfo.msg.u.xpmsg_flush_region;
|
||||
volatile struct xpmsg_flush_region *p = &cpuinfo.msg.u.xpmsg_flush_region;
|
||||
int ctx = getcontext();
|
||||
|
||||
setcontext(p->ctx);
|
||||
|
|
@ -369,7 +376,7 @@ nmi_soft(tf)
|
|||
}
|
||||
case XPMSG_DEMAP_TLB_CONTEXT:
|
||||
{
|
||||
struct xpmsg_flush_context *p = &cpuinfo.msg.u.xpmsg_flush_context;
|
||||
volatile struct xpmsg_flush_context *p = &cpuinfo.msg.u.xpmsg_flush_context;
|
||||
int ctx = getcontext();
|
||||
|
||||
setcontext(p->ctx);
|
||||
|
|
@ -384,7 +391,46 @@ nmi_soft(tf)
|
|||
cpuinfo.flags |= CPUFLG_GOTMSG;
|
||||
#endif
|
||||
}
|
||||
|
||||
#if defined(MULTIPROCESSOR)
|
||||
/*
|
||||
* Respond to an xcall() request from another CPU.
|
||||
*/
|
||||
static void xcallintr(void *v)
|
||||
{
|
||||
struct cpu_info *cpi = cpus[cpuinfo.ci_cpuid];
|
||||
|
||||
switch (cpi->msg.tag) {
|
||||
case XPMSG_PAUSECPU:
|
||||
{
|
||||
#if defined(DDB)
|
||||
struct trapframe *tf = v;
|
||||
volatile db_regs_t regs;
|
||||
|
||||
regs.db_tf = *tf;
|
||||
regs.db_fr = *(struct frame *)tf->tf_out[6];
|
||||
cpi->ci_ddb_regs = ®s;
|
||||
#endif
|
||||
cpi->flags |= CPUFLG_PAUSED|CPUFLG_GOTMSG;
|
||||
while (cpi->flags & CPUFLG_PAUSED) /**/;
|
||||
#if defined(DDB)
|
||||
cpi->ci_ddb_regs = NULL;
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
case XPMSG_FUNC:
|
||||
{
|
||||
volatile struct xpmsg_func *p = &cpuinfo.msg.u.xpmsg_func;
|
||||
|
||||
if (p->func)
|
||||
p->retval = (*p->func)(p->arg0, p->arg1, p->arg2, p->arg3);
|
||||
break;
|
||||
}
|
||||
}
|
||||
cpi->flags |= CPUFLG_GOTMSG;
|
||||
}
|
||||
#endif /* MULTIPROCESSOR */
|
||||
#endif /* SUN4M || SUN4D */
|
||||
|
||||
/*
|
||||
* Level 15 interrupts are special, and not vectored here.
|
||||
|
|
@ -617,6 +663,10 @@ softintr_init()
|
|||
{
|
||||
|
||||
softnet_cookie = softintr_establish(IPL_SOFTNET, softnet, NULL);
|
||||
#if defined(MULTIPROCESSOR) && (defined(SUN4M) || defined(SUN4D))
|
||||
/* Establish a standard soft interrupt handler for cross calls */
|
||||
xcall_cookie = softintr_establish(13, xcallintr, NULL);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
Loading…
Reference in New Issue