Add support for caches where the data cache is fully coherent, and
either requires flushing either only when the I cache ops are used or not at all. Currently only used by MIPS32/MIPS64 cache code.
This commit is contained in:
simonb
parent
4ec8d15e0d
commit
2c1a832f25
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@ -1,4 +1,4 @@
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/* $NetBSD: cache.h,v 1.4 2002/11/09 19:34:40 thorpej Exp $ */
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/* $NetBSD: cache.h,v 1.5 2002/12/17 12:04:29 simonb Exp $ */
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/*
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* Copyright 2001 Wasabi Systems, Inc.
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@ -134,11 +134,21 @@ struct mips_cache_ops {
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void (*mco_pdcache_inv_range)(vaddr_t, vsize_t);
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void (*mco_pdcache_wb_range)(vaddr_t, vsize_t);
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/* These are called only by the (mipsNN) icache functions. */
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void (*mco_intern_pdcache_wbinv_all)(void);
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void (*mco_intern_pdcache_wbinv_range_index)(vaddr_t, vsize_t);
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void (*mco_intern_pdcache_wb_range)(vaddr_t, vsize_t);
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void (*mco_sdcache_wbinv_all)(void);
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void (*mco_sdcache_wbinv_range)(vaddr_t, vsize_t);
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void (*mco_sdcache_wbinv_range_index)(vaddr_t, vsize_t);
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void (*mco_sdcache_inv_range)(vaddr_t, vsize_t);
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void (*mco_sdcache_wb_range)(vaddr_t, vsize_t);
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/* These are called only by the (mipsNN) icache functions. */
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void (*mco_intern_sdcache_wbinv_all)(void);
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void (*mco_intern_sdcache_wbinv_range_index)(vaddr_t, vsize_t);
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void (*mco_intern_sdcache_wb_range)(vaddr_t, vsize_t);
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};
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#ifdef _KERNEL
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@ -195,18 +205,18 @@ extern u_int mips_cache_prefer_mask;
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*/
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#define mips_cache_indexof(x) (((vaddr_t)(x)) & mips_cache_alias_mask)
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#define __mco_noargs(x) \
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#define __mco_noargs(prefix, x) \
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do { \
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(*mips_cache_ops.mco_p ## x )(); \
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if (*mips_cache_ops.mco_s ## x ) \
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(*mips_cache_ops.mco_s ## x )(); \
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(*mips_cache_ops.mco_ ## prefix ## p ## x )(); \
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if (*mips_cache_ops.mco_ ## prefix ## s ## x ) \
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(*mips_cache_ops.mco_ ## prefix ## s ## x )(); \
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} while (/*CONSTCOND*/0)
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#define __mco_2args(x, a, b) \
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#define __mco_2args(prefix, x, a, b) \
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do { \
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(*mips_cache_ops.mco_p ## x )((a), (b)); \
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if (*mips_cache_ops.mco_s ## x ) \
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(*mips_cache_ops.mco_s ## x )((a), (b)); \
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(*mips_cache_ops.mco_ ## prefix ## p ## x )((a), (b)); \
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if (*mips_cache_ops.mco_ ## prefix ## s ## x ) \
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(*mips_cache_ops.mco_ ## prefix ## s ## x )((a), (b)); \
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} while (/*CONSTCOND*/0)
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#define mips_icache_sync_all() \
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@ -219,21 +229,37 @@ do { \
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(*mips_cache_ops.mco_icache_sync_range_index)((v), (s))
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#define mips_dcache_wbinv_all() \
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__mco_noargs(dcache_wbinv_all)
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__mco_noargs(, dcache_wbinv_all)
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#define mips_dcache_wbinv_range(v, s) \
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__mco_2args(dcache_wbinv_range, (v), (s))
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__mco_2args(, dcache_wbinv_range, (v), (s))
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#define mips_dcache_wbinv_range_index(v, s) \
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__mco_2args(dcache_wbinv_range_index, (v), (s))
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__mco_2args(, dcache_wbinv_range_index, (v), (s))
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#define mips_dcache_inv_range(v, s) \
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__mco_2args(dcache_inv_range, (v), (s))
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__mco_2args(, dcache_inv_range, (v), (s))
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#define mips_dcache_wb_range(v, s) \
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__mco_2args(dcache_wb_range, (v), (s))
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__mco_2args(, dcache_wb_range, (v), (s))
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/*
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* Private D-cache functions only called from (currently only the
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* mipsNN) I-cache functions.
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*/
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#define mips_intern_dcache_wbinv_all() \
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__mco_noargs(intern_, dcache_wbinv_all)
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#define mips_intern_dcache_wbinv_range_index(v, s) \
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__mco_2args(intern_, dcache_wbinv_range_index, (v), (s))
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#define mips_intern_dcache_wb_range(v, s) \
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__mco_2args(intern_, dcache_wb_range, (v), (s))
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void mips_config_cache(void);
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void mips_dcache_compute_align(void);
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#include <mips/cache_mipsNN.h>
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#endif /* _KERNEL */
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu.h,v 1.68 2002/11/24 07:26:04 simonb Exp $ */
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/* $NetBSD: cpu.h,v 1.69 2002/12/17 12:04:29 simonb Exp $ */
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/*-
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* Copyright (c) 1992, 1993
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@ -163,6 +163,8 @@ extern int mips3_pg_cached;
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#define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */
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#define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */
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#define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */
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#define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */
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#define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */
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#define MIPS_NOT_SUPP 0x8000
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#ifdef _LKM
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@ -1,4 +1,4 @@
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/* $NetBSD: cache.c,v 1.14 2002/11/24 07:41:30 simonb Exp $ */
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/* $NetBSD: cache.c,v 1.15 2002/12/17 12:04:30 simonb Exp $ */
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/*
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* Copyright 2001, 2002 Wasabi Systems, Inc.
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@ -825,10 +825,8 @@ mips3_get_cache_config(int csizebase)
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#if defined(MIPS32) || defined(MIPS64)
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#ifdef MIPS_DISABLE_L1_CACHE
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static void cache_noop(void);
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static void cache_noop(void) __attribute__((__unused__));
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static void cache_noop(void) {}
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#endif
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static void
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mips_config_cache_modern(void)
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@ -957,36 +955,47 @@ mips_config_cache_modern(void)
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switch (mips_pdcache_line_size) {
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case 16:
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mips_cache_ops.mco_pdcache_wbinv_all =
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mips_cache_ops.mco_intern_pdcache_wbinv_all =
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mipsNN_pdcache_wbinv_all_16;
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mips_cache_ops.mco_pdcache_wbinv_range =
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mipsNN_pdcache_wbinv_range_16;
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mips_cache_ops.mco_pdcache_wbinv_range_index =
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mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
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mipsNN_pdcache_wbinv_range_index_16;
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mips_cache_ops.mco_pdcache_inv_range =
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mipsNN_pdcache_inv_range_16;
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mips_cache_ops.mco_pdcache_wb_range =
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mips_cache_ops.mco_intern_pdcache_wb_range =
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mipsNN_pdcache_wb_range_16;
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break;
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case 32:
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mips_cache_ops.mco_pdcache_wbinv_all =
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mips_cache_ops.mco_intern_pdcache_wbinv_all =
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mipsNN_pdcache_wbinv_all_32;
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mips_cache_ops.mco_pdcache_wbinv_range =
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mipsNN_pdcache_wbinv_range_32;
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mips_cache_ops.mco_pdcache_wbinv_range_index =
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mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
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mipsNN_pdcache_wbinv_range_index_32;
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mips_cache_ops.mco_pdcache_inv_range =
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mipsNN_pdcache_inv_range_32;
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mips_cache_ops.mco_pdcache_wb_range =
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mips_cache_ops.mco_intern_pdcache_wb_range =
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mipsNN_pdcache_wb_range_32;
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break;
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#ifdef MIPS_DISABLE_L1_CACHE
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case 0:
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mips_cache_ops.mco_pdcache_wbinv_all = (void *)cache_noop;
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mips_cache_ops.mco_intern_pdcache_wbinv_all =
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(void *)cache_noop;
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mips_cache_ops.mco_pdcache_wbinv_range = (void *)cache_noop;
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mips_cache_ops.mco_pdcache_wbinv_range_index =
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(void *)cache_noop;
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mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
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(void *)cache_noop;
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mips_cache_ops.mco_pdcache_inv_range = (void *)cache_noop;
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mips_cache_ops.mco_pdcache_wb_range = (void *)cache_noop;
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mips_cache_ops.mco_intern_pdcache_wb_range = (void *)cache_noop;
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break;
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#endif
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default:
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@ -995,5 +1004,29 @@ mips_config_cache_modern(void)
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}
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mipsNN_cache_init(cfg, cfg1);
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if (mips_cpu_flags &
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(CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_I_D_CACHE_COHERENT)) {
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#ifdef CACHE_DEBUG
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printf(" Dcache is coherent\n");
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#endif
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mips_cache_ops.mco_pdcache_wbinv_all = (void *)cache_noop;
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mips_cache_ops.mco_pdcache_wbinv_range = (void *)cache_noop;
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mips_cache_ops.mco_pdcache_wbinv_range_index =
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(void *)cache_noop;
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mips_cache_ops.mco_pdcache_inv_range = (void *)cache_noop;
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mips_cache_ops.mco_pdcache_wb_range = (void *)cache_noop;
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}
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if (mips_cpu_flags & CPU_MIPS_I_D_CACHE_COHERENT) {
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#ifdef CACHE_DEBUG
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printf(" Icache is coherent against Dcache\n");
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#endif
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mips_cache_ops.mco_intern_pdcache_wbinv_all =
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(void *)cache_noop;
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mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
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(void *)cache_noop;
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mips_cache_ops.mco_intern_pdcache_wb_range =
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(void *)cache_noop;
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}
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}
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#endif /* MIPS32 || MIPS64 */
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@ -1,4 +1,4 @@
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/* $NetBSD: cache_mipsNN.c,v 1.6 2002/11/24 07:41:31 simonb Exp $ */
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/* $NetBSD: cache_mipsNN.c,v 1.7 2002/12/17 12:04:30 simonb Exp $ */
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/*
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* Copyright 2001 Wasabi Systems, Inc.
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@ -120,7 +120,7 @@ mipsNN_icache_sync_all_16(void)
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* worry about the N different "ways".
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*/
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mips_dcache_wbinv_all();
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mips_intern_dcache_wbinv_all();
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while (va < eva) {
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cache_r4k_op_32lines_16(va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
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@ -143,7 +143,7 @@ mipsNN_icache_sync_all_32(void)
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* worry about the N different "ways".
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*/
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mips_dcache_wbinv_all();
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mips_intern_dcache_wbinv_all();
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while (va < eva) {
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cache_r4k_op_32lines_32(va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
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@ -161,7 +161,7 @@ mipsNN_icache_sync_range_16(vaddr_t va, vsize_t size)
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eva = round_line16(va + size);
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va = trunc_line16(va);
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mips_dcache_wb_range(va, (eva - va));
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mips_intern_dcache_wb_range(va, (eva - va));
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while ((eva - va) >= (32 * 16)) {
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cache_r4k_op_32lines_16(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV);
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@ -184,7 +184,7 @@ mipsNN_icache_sync_range_32(vaddr_t va, vsize_t size)
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eva = round_line32(va + size);
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va = trunc_line32(va);
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mips_dcache_wb_range(va, (eva - va));
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mips_intern_dcache_wb_range(va, (eva - va));
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while ((eva - va) >= (32 * 32)) {
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cache_r4k_op_32lines_32(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV);
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@ -223,7 +223,7 @@ mipsNN_icache_sync_range_index_16(vaddr_t va, vsize_t size)
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stride = picache_stride;
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loopcount = picache_loopcount;
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mips_dcache_wbinv_range_index(va, (eva - va));
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mips_intern_dcache_wbinv_range_index(va, (eva - va));
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while ((eva - va) >= (8 * 16)) {
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tmpva = va;
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@ -266,7 +266,7 @@ mipsNN_icache_sync_range_index_32(vaddr_t va, vsize_t size)
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stride = picache_stride;
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loopcount = picache_loopcount;
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mips_dcache_wbinv_range_index(va, (eva - va));
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mips_intern_dcache_wbinv_range_index(va, (eva - va));
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while ((eva - va) >= (8 * 32)) {
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tmpva = va;
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