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Disable `unimplemented flush' traps during boot. Keep it disabled on

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non-MULTIPROCESSOR kernels.
This commit is contained in:
pk 2002-12-15 15:01:08 +00:00
parent e9628b7102
commit 9313f9570d
2 changed files with 14 additions and 3 deletions
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6
sys/arch/sparc/sparc/cache.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cache.c,v 1.63 2002/07/29 06:39:41 grant Exp $ */
/* $NetBSD: cache.c,v 1.64 2002/12/15 15:01:08 pk Exp $ */
/*
* Copyright (c) 1996
@ -230,7 +230,11 @@ hypersparc_cache_enable()
* Enable instruction cache and, on single-processor machines,
* disable `Unimplemented Flush Traps'.
*/
#if defined(MULTIPROCESSOR)
v = HYPERSPARC_ICCR_ICE | (ncpu == 1 ? HYPERSPARC_ICCR_FTD : 0);
#else
v = HYPERSPARC_ICCR_ICE | HYPERSPARC_ICCR_FTD);
#endif
wrasr(v, HYPERSPARC_ASRNUM_ICCR);
}

11
sys/arch/sparc/sparc/cpu.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.c,v 1.137 2002/11/29 08:29:57 pk Exp $ */
/* $NetBSD: cpu.c,v 1.138 2002/12/15 15:01:08 pk Exp $ */
/*
* Copyright (c) 1996
@ -1348,8 +1348,15 @@ cpumatch_hypersparc(sc, mp, node)
int node;
{
sc->cpu_type = CPUTYP_HS_MBUS;/*XXX*/
if (node == 0)
if (node == 0) {
/* Flush I-cache */
sta(0, ASI_HICACHECLR, 0);
/* Disable `unimplemented flush' traps during boot-up */
wrasr(rdasr(HYPERSPARC_ASRNUM_ICCR) | HYPERSPARC_ICCR_FTD,
HYPERSPARC_ASRNUM_ICCR);
}
}
void