(which disables the interrupts) is *not* a good idea. k0 (and k1) is used
by the kernel code such as the TLB miss handler, and the interrupt entry.
If an interrupt occurs after loading k0 and before the SR gets interrupts
disabled, k0 will be clobbered and when used to load the PC on exit from
the exception handler, results in various hangs and crashes.
don't stomp on the return address in k0. Also, don't need to account
for any load delays, as the last register restored (gp) isn't used in
the subsequent instruction.
Shuichiro URATA <ur@a-r.org> makes kernel softfloat emulation code.
http://www.a-r.org/~ur/softfloat1116.diff.gz
is Patch for
sys/arch/mips/conf/files.mips
sys/arch/mips/mips/fp.S
sys/arch/mips/mips/fpemu.c
sys/arch/mips/mips/genassym.cf
sys/arch/mips/mips/locore.S
sys/arch/mips/mips/mips_machdep.c
sys/arch/mips/mips/process_machdep.c
sys/arch/mips/mips/trap.c
sys/arch/mips/mips/vm_machdep.c
After apply this patch,pmax package binary works on hpcmips!
Use flags (formerly access_type) to set page reference/modified status.
Don't use the PG_CLEAN flag from the UVM when checking to see if a
writeable page has been marked as modified.
When updating page status to modified from the UTLBmiss handler, set
the referenced bit in addition to the modified bit.
Page mod/ref status is stored in the pv header, and needs to be copied to
the following entry when removing the head entry, otherwise the status
will be lost (oops!).
Move the common MIPS3 cache flush into pmap_remove_pv() and eliminate the
unnecessary testing of the return value when only compiled for MIPS1.
If the pv entry had the cache inhibited, and we remove the last cache index
alias conflict, restore caching on the mappings for that entry.
Eliminate possible extra cache flushing inherited from the pica pmap: it
was doing the flush when the head entry was being removed - not just the last
entry. Now the flush is done only when the last mapping has been removed.
Also make sure the secondary cache gets flushed [MIPS3 cache flushing needs
to be re-thought/re-done someday].
Update comment for pmap_remove_pv() to reflect these changes.
original debug output was printing the argument to pmap_create(), but
pmap_create() no longer has an argument. The incorrect change now prints
an un-initialized pointer. Change to just print out the function name.
cache. With secondary cache, the CPU will detect cache coherency errors
and the Virtual Coherency Exception handler will flush the appropriate
cache lines to maintain cache coherency. This allows much better
performance than inhibiting the cache for the entire page. This is
very noticable when shared library mappings occur with incompatible
mappings, since there's a very likely chance the mappings will remain
for long periods of time. Systems without secondary cache will still
have the cache inhibited, so there will still be performance issues if
shared libraries don't get mmaped() on correct memory alignments.
This fixes the current problems on DECstations using the R4x00 getting
coredumped programs.
Support VR4100.
Support 16KB page.
Support CPU without FPU.
Fix virtual alias problem(physio() case).
[new options]
options MIPS3_4100 /* VR4100 core */
options MIPS_16K_PAGE /* enable kernel support for 16k pages */
options SOFTFLOAT /* No FPU; avoid touching FPU registers */
big-endian. i386, pc532 and vax still include <machine/byte_swap.h>
and define macros for the {n,h}to{h,n}*() functions. mips also
defines some endian-independent assembly-code aliases for unaligned
memory accesses.
in kernel mode after master interrupt (MIPS_SR_INT_IE) disabled. Tons
of appreciation for Noriyuki Soda and Masanari Tsubai for almost full
time help to spot of the issue.
- remove "need-flag" for mac68k esp driver, as it is not used in anywhere
and conflicts with IPsec ESP header.
This should be the only MD change in IPv6 support, except kernel config file.
Very sorry if you have any compilation problem with it (I believe it is okay).
If your favorite arch is not included in here, please add a
call to ip6intr() from softintr handle.
either endian. Not a perfect solution which would be revealed on
a certain condition when va_arg() is applied to magical struct
arguments passed by value. format_bytes() is now saved. With the
help from Noriyuki Soda and Masanari Tsubai.
TLBUpdate() routine is used for dual purposes. In TLBmod case, just ok
to call 'tlbwi' (as designed). Result in saving of extraneous execution
path. MIPS1 only this moment.
(correct name, vax?) replacing mips1_TLBFlushAddr and mips1_TLBUpdate,
respectively. New codes always use current ASID holded in EntryHi
register. In most occations, the register already contains a necessary
value before (re-)written, ugh. 'sva | asid' ops for their arguments are
now verbose, to be removed when MIPS3 side changes are done.
'pm_asid' member of 'pmap' structure is assigned a new value after
uvmspace_alloc() provides afresh pmap.
- ASID generation number 0 is not a reserved value anymore.
processor is one of processors with no 'referenced bit' nor 'modified bit'
processor machinary. Those functions are implemented combining two
hardware bits, 'dirty bit' and 'valid bit', with TLBmod exception handler.
per process user spaces, replacing mips1_TBLFlush(). This reserves
kernel space TLB entries when TLBPID generation number about to wrap.
- Correct comments a bit, nuke unused routines.
initialization code.
- Abandon mips_init_proc0() and do the 4 lines straightly in MD mach_init().
- Restore a block of code accidentally lost in prevous commit.
- Change the term 'tlbpid' to a MIPS3 nomenclature 'asid'.
- Hide PTE size exposures by symbolic names in locore.S
the child inherits the stack pointer from the parent (traditional
behavior). Like the signal stack, the stack area is secified as
a low address and a size; machine-dependent code accounts for stack
direction.
This is required for clone(2).
_splraise, _spllower, _splset, _splget, _setsoftintr, _clrsoftintr, _splnone.
They manipulate MIPS processor's 8 interrupt sources and are used
as building blocks for NetBSD spl(9) kernel interface. Note that
MIPS processor doesn't enforce inclusive 'interrupt levels' found
in other processors, then the hierarchal nature of IPL must be
implemented by composing MIPS processor interrupt masks appropriately.
With the simplest target port in which small number of devices are
independently assigned with 6 external interrupt signal lines,
spl(9) kernel interface will be implemented with #define's of
processor interrupt controls mentioned above. In more general
cases, in which target computers have many devices and 'system
registers' indicating pending interrupt sources at any moment,
spl(9) will be implemented with more complex machinary manipulating
processor interrupts and system registers in target port dependent
ways.
- Nuke unused code and reorder locore definitions. XXX Following
routines will be replaced with C language version; setrunqueue,
remrunqueue, switchfpregs, savefpregs, MachFPInterrupt.
- ALIAS() is not needed, use XLEAF() or XNESTED() instead
- use AENT() instead of .aent
- _END_LABEL() is not needed (and was wrong)
- define ALEAF(), NLEAF(), NON_LEAF(), NNON_LEAF() by
XLEAF(), LEAF_NONPROFILE(), NESTED(), NESTED_NONPROFILE()
* Map the message buffer with access_type = VM_PROT_READ|VM_PROT_WRITE `just
because'.
* Map the file system buffers with access_type = VM_PROT_READ|VM_PROT_WRITE to
avoid possible problems with pagemove().
* Do not use VM_PROT_EXEC with either of the above.
* Map pages for /dev/mem with access_type = prot. Also, DO NOT use
pmap_kenter() for this, as we DO NOT want to lose modification information.
* Map pages in dumpsys() with VM_PROT_READ.
* Map pages in m68k mappedcopyin()/mappedcopyout() and writeback() with
access_type = prot.
* For now, bus_dma*(), pmap_map(), vmapbuf(), and similar functions still use
access_type = 0. This should probably be revisited.
allocated from a pool, and the MIPS and Alpha use KSEG to map pool
pages. So, mb_map wasn't actually being used. Saves around 4MB of
kernel virtual address space in a typical configuration.
Garbage-collect the related VM_MBUF_SIZE constant.
pointer to just underneath _start. Allows bootblocks (or other kernel
calling programs) to pass more than 4 arguments if it sets up the stack
properly.
The 4kB figure may be overkill - on the pmax it only needs to be a dozen
of so bytes.
tlbmod exception panics. This appears to have been incorrect even in the pica
pmap.c, which I pulled in for the pmax. Fixes Xcfbpmax crashes on R40x0
systems with sfb framebuffer.
Fix resident_count tracking so it doesn't go negative. UVM will change a
page mapping without removing the original mapping. That was causing a
problem early on when getting UVM working on the mips, and the explicit
pmap_remove() done by pmap_enter() was decrementing the resident_count.
Do the pmap_remove() first, then check if the current mapping is not valid
and increment the resident_count.
the *initial* stack pointer. The proc0 stack is being used by proc0 (i.e.
uvm_scheduler). This had been working because switch_exit() wasn't
overwriting any critical areas of the stack - unless kernel profiling
was turned on.
on 64 bit register that's not correctly signed extended. The R4x00 support
works again on DECstations. A similar change to the XTLBMiss handler probably
needs to be made, but I have not done that since I am unable to test any
changes to that.
Also re-order a couple of instructions to allow for delay with mfc0.
- Fix an error in mips3_cpu_switch_resume(); ASID was not set correctly.
- Remove global variable 'curpcb' reference in mips1_proc_trampoline().
- Restore 'cpuregs.h'.
