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TX3912/22 support. ENABLE_MIPS_TX3900 enables it.

This commit is contained in:
uch 1999-11-29 11:12:12 +00:00
parent c3f48a34ce
commit 347ea4cd91
6 changed files with 239 additions and 9 deletions
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6
sys/arch/mips/include/cpuregs.h
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@ -1,4 +1,4 @@
/* $NetBSD: cpuregs.h,v 1.23 1999/09/25 00:00:37 shin Exp $ */
/* $NetBSD: cpuregs.h,v 1.24 1999/11/29 11:12:12 uch Exp $ */
/*
* Copyright (c) 1992, 1993
@ -647,4 +647,8 @@
#define MIPS_R3TOSH 0x22 /* ? Toshiba R3000 based FPU ISA I */
#define MIPS_R3NKK 0x23 /* ? NKK R3000 based FPU ISA I */
#ifdef ENABLE_MIPS_TX3900
#include <mips/r3900regs.h>
#endif
#endif /* _MIPS_CPUREGS_H_ */

6
sys/arch/mips/include/vmparam.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: vmparam.h,v 1.15 1999/04/24 08:10:38 simonb Exp $ */
/* $NetBSD: vmparam.h,v 1.16 1999/11/29 11:12:12 uch Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@ -134,7 +134,11 @@
#define VM_MAXUSER_ADDRESS ((vaddr_t)0x80000000)
#define VM_MAX_ADDRESS ((vaddr_t)0x80000000)
#define VM_MIN_KERNEL_ADDRESS ((vaddr_t)0xC0000000)
#ifdef ENABLE_MIPS_TX3900
#define VM_MAX_KERNEL_ADDRESS ((vaddr_t)0xFF000000)
#else
#define VM_MAX_KERNEL_ADDRESS ((vaddr_t)0xFFFFC000)
#endif
/* virtual sizes (bytes) for various kernel submaps */
#define VM_KMEM_SIZE (NKMEMCLUSTERS*CLBYTES)

4
sys/arch/mips/mips/db_interface.c
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@ -1,4 +1,4 @@
/* $NetBSD: db_interface.c,v 1.21 1999/10/28 06:54:16 lukem Exp $ */
/* $NetBSD: db_interface.c,v 1.22 1999/11/29 11:12:13 uch Exp $ */
/*
* Mach Operating System
@ -284,7 +284,7 @@ db_tlbdump_cmd(addr, have_addr, count, modif)
int i;
extern void mips1_TLBRead __P((int, struct mips1_tlb *));
for (i = 0; i < MIPS1_TLB_NUM_TLB_ENTRIES; i++) {
for (i = 0; i < mips_num_tlb_entries; i++) {
mips1_TLBRead(i, &tlb);
db_printf("TLB%c%2d Hi 0x%08x Lo 0x%08x",
(tlb.tlb_lo & MIPS1_PG_V) ? ' ' : '*',

12
sys/arch/mips/mips/locore.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.S,v 1.79 1999/11/18 06:47:49 jun Exp $ */
/* $NetBSD: locore.S,v 1.80 1999/11/29 11:12:13 uch Exp $ */
/*
* Copyright (c) 1992, 1993
@ -99,6 +99,16 @@ _C_LABEL(kernel_text):
#ifdef __GP_SUPPORT__
la gp, _C_LABEL(_gp)
#endif
#ifdef R3900_CACHE_DISABLE
li t0, ~(R3900_CONFIG_ICE|R3900_CONFIG_DCE)
mfc0 t1, R3900_COP_0_CONFIG
and t1, t0, t1
nop
mtc0 t1, R3900_COP_0_CONFIG
nop
#endif /* R3900_CACHE_DISABLE */
#ifdef SOFTFLOAT /* No FPU; avoid touching FPU registers */
li t0, 0 # Disable interrupts and
mtc0 t0, MIPS_COP_0_STATUS # the fp coprocessor

180
sys/arch/mips/mips/locore_mips1.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore_mips1.S,v 1.16 1999/11/10 08:06:11 nisimura Exp $ */
/* $NetBSD: locore_mips1.S,v 1.17 1999/11/29 11:12:14 uch Exp $ */
/*
* Copyright (c) 1992, 1993
@ -1204,7 +1204,7 @@ END(mips1_TLBGetPID)
*
*----------------------------------------------------------------------------
*/
#ifndef ENABLE_MIPS_TX3900
/*----------------------------------------------------------------------------
*
@ -1536,7 +1536,183 @@ LEAF(mips1_wbflush)
j ra
nop
END(mips1_wbflush)
#else /* !ENABLE_MIPS_TX3900 */
/*
* The differences between R3900 and R3000.
* 1. Cache system
* TX3912 I-cache 4KB/16B direct mapped
* D-cache 1KB/4B 2-way sa
* TX3922 I-cache 16KB/16B 2-way sa
* D-cache 8KB/16B 2-way sa
* (mips/mips/locore_mips1.S)
*
* 2. Coprocessor1
* 2.1 cache operation.
* R3900 uses MIPSIII cache op like method.
* 2.2 R3900 specific CP0 register.
* (mips/include/r3900regs.h overrides cpuregs.h)
* 2.3 # of TLB entries
* TX3912 32 entries
* TX3922 64 entries
*
* 3. System address map
* kseg2 0xff000000-0xfffeffff is reserved.
* (mips/include/vmparam.h)
*
* If defined both MIPS1 and ENABLE_MIPS_TX3900, it generates kernel for
* R3900. If defined MIPS1 only, No R3900 feature include.
*/
/*
* void mips1_ConfigCache(void)
*/
LEAF(mips1_ConfigCache)
mfc0 t0, R3900_COP_0_CONFIG
li t1, R3900_CONFIG_ICS_MASK
and t1, t1, t0
srl t1, t1, R3900_CONFIG_ICS_SHIFT
li t2, R3900_MIN_CACHE_SIZE
sllv t1, t2, t1
sw t1, _C_LABEL(mips_L1ICacheSize)
li t1, R3900_CONFIG_DCS_MASK
and t1, t1, t0
srl t1, t1, R3900_CONFIG_DCS_SHIFT
li t2, R3900_MIN_CACHE_SIZE
sllv t1, t2, t1
sw t1, _C_LABEL(mips_L1DCacheSize)
j ra
nop
END(mips1_ConfigCache)
/*
* R3900 2-way set-associative, line size 4byte(3900)/16byte(3920)
* void mips1_FlushDCache(vaddr_t addr, vsize_t len)
*/
LEAF(mips1_FlushDCache)
lw t0, mips_L1DCacheLSize
addu a1, a1, a0 # compute ending address
1:
R3900_CACHE(R3900_CACHE_D_HITINVALIDATE, 0, CPUREG_A0)
addu a0, a0, t0
bne a0, a1, 1b
nop
j ra
nop
END(mips1_FlushDCache)
/*
* R3900 direct-mapped/2-way set-associative line size 16byte
* void mips1_FlushICache(vaddr_t addr, vsize_t len)
*/
LEAF(mips1_FlushICache)
mfc0 t0, MIPS_COP_0_STATUS # Save SR
nop
mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts.
nop
# Disable I-cache
li t1, ~R3900_CONFIG_ICE
mfc0 t2, R3900_COP_0_CONFIG
and t1, t1, t2
nop
mtc0 t1, R3900_COP_0_CONFIG
j 2f # stop streaming
nop
2:
# Flush I-cache
addu a1, 127
srl a1, a1, 7 # Number of unrolled loops
3:
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 0, CPUREG_A0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 16, CPUREG_A0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 32, CPUREG_A0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 48, CPUREG_A0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 64, CPUREG_A0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 80, CPUREG_A0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 96, CPUREG_A0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 112, CPUREG_A0)
addu a1, -1
bne a1, zero, 3b
addu a0, 128
# Enable I-cache
nop
mtc0 t2, R3900_COP_0_CONFIG
nop
mtc0 t0, MIPS_COP_0_STATUS # enable interrupts
j ra # return and run cached
nop
END(mips1_FlushICache)
/*
*
* void mips_FlushCache(void)
*/
LEAF(mips1_FlushCache)
lw t1, mips_L1ICacheSize
lw t2, mips_L1DCacheSize
# lw t3, mips_L1ICacheLSize
# lw t4, mips_L1DCacheLSize
nop
mfc0 t7, MIPS_COP_0_STATUS # Save SR
nop
mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts.
nop
# Disable I-cache
li t5, ~R3900_CONFIG_ICE
mfc0 t6, R3900_COP_0_CONFIG
and t5, t5, t6
nop
mtc0 t5, R3900_COP_0_CONFIG
j 2f # stop streaming
nop
2:
# Flush cache
li t0, MIPS_KSEG0_START
addu t1, t0, t1 # End address
subu t1, t1, 128
3:
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 0, CPUREG_T0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 16, CPUREG_T0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 32, CPUREG_T0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 48, CPUREG_T0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 64, CPUREG_T0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 80, CPUREG_T0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 96, CPUREG_T0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 112, CPUREG_T0)
bne t0, t1, 3b
addu t0, t0, 128
# Flush D-cache
la t0, dummy_buffer
addu t1, t0, t2 # End address
4:
lw t2, 0(t0)
bne t1, t0, 4b
addiu t0, t0, 4
# Enable I-cache
nop
mtc0 t6, R3900_COP_0_CONFIG
nop
mtc0 t7, MIPS_COP_0_STATUS # enable interrupts
j ra # return and run cached
nop
END(mips1_FlushCache)
LEAF(mips1_wbflush)
nop
sync
nop
j ra
nop
END(mips1_wbflush)
.comm dummy_buffer, R3900_MAX_DCACHE_SIZE
#endif /* !ENABLE_MIPS_TX3900 */
/*
* mips1_proc_trampoline
*

40
sys/arch/mips/mips/mips_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mips_machdep.c,v 1.59 1999/11/18 06:47:49 jun Exp $ */
/* $NetBSD: mips_machdep.c,v 1.60 1999/11/29 11:12:14 uch Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@ -52,7 +52,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.59 1999/11/18 06:47:49 jun Exp $");
__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.60 1999/11/29 11:12:14 uch Exp $");
#include "opt_compat_netbsd.h"
#include "opt_compat_ultrix.h"
@ -131,6 +131,9 @@ int default_pg_mask = 0x00001800;
#endif
#ifdef MIPS1
#ifdef ENABLE_MIPS_TX3900
int r3900_icache_direct;
#endif
/*
* MIPS-I (r2000 and r3000) locore-function vector.
*/
@ -356,6 +359,27 @@ mips_vector_init()
cpu_arch = 1;
mips_num_tlb_entries = MIPS1_TLB_NUM_TLB_ENTRIES;
break;
#ifdef ENABLE_MIPS_TX3900
case MIPS_TX3900:
cpu_arch = 1;
switch (cpu_id.cpu.cp_majrev) {
default:
panic("not supported revision");
case 1: /* TX3912 */
mips_num_tlb_entries = R3900_TLB_NUM_TLB_ENTRIES;
r3900_icache_direct = 1;
mips_L1ICacheLSize = 16;
mips_L1DCacheLSize = 4;
break;
case 3: /* TX3922 */
mips_num_tlb_entries = R3920_TLB_NUM_TLB_ENTRIES;
r3900_icache_direct = 0;
mips_L1ICacheLSize = 16;
mips_L1DCacheLSize = 16;
break;
}
break;
#endif /* ENABLE_MIPS_TX3900 */
#endif /* MIPS1 */
#ifdef MIPS3
@ -462,7 +486,11 @@ struct pridtab cputab[] = {
{ MIPS_R8000, "MIPS R8000 Blackbird/TFP CPU", 4 },
{ MIPS_R4600, "QED R4600 Orion CPU", 3 },
{ MIPS_R4700, "QED R4700 Orion CPU", 3 },
#ifdef ENABLE_MIPS_TX3900
{ MIPS_TX3900, "Toshiba TX3900 CPU", 1 }, /* see below */
#else
{ MIPS_TX3900, "Toshiba TX3900 or QED R4650 CPU", 1 }, /* see below */
#endif
{ MIPS_R5000, "MIPS R5000 CPU", 4 },
{ MIPS_RC32364, "IDT RC32364 CPU", 3 },
{ MIPS_RM5230, "QED RM5200 CPU", 4 },
@ -539,8 +567,16 @@ cpu_identify()
printf("cpu0: ");
#ifdef MIPS1
if (cpu_arch == 1) {
#ifdef ENABLE_MIPS_TX3900
printf("%dKB/%dB Instruction %s, %dKB/%dB Data 2-way set associative, %d TLB entries",
mips_L1ICacheSize / 1024, mips_L1ICacheLSize,
r3900_icache_direct ? "direct mapped" : "2-way set associative",
mips_L1DCacheSize / 1024, mips_L1DCacheLSize,
mips_num_tlb_entries);
#else /* ENABLE_MIPS_TX3900 */
printf("%dKB Instruction, %dKB Data, direct mapped cache",
mips_L1ICacheSize / 1024, mips_L1DCacheSize / 1024);
#endif /* ENABLE_MIPS_TX3900 */
}
#endif
#ifdef MIPS3