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- MIPS processors do not impose inclusive (nesting) interrupt levels with 

their interrupt lines.  The notion and implemention of 'spl' are left
for how target ports approach to it.
This commit is contained in:
nisimura 1999-04-26 09:42:14 +00:00
parent 9e798fbe20
commit 56a9b84b91
1 changed files with 1 additions and 14 deletions
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15
sys/arch/mips/include/cpuregs.h
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@ -1,4 +1,4 @@
/* $NetBSD: cpuregs.h,v 1.20 1999/04/24 08:10:34 simonb Exp $ */
/* $NetBSD: cpuregs.h,v 1.21 1999/04/26 09:42:14 nisimura Exp $ */
/*
* Copyright (c) 1992, 1993
@ -244,19 +244,6 @@
#define MIPS_SOFT_INT_MASK_1 0x0200
#define MIPS_SOFT_INT_MASK_0 0x0100
/*
* nesting interrupt masks.
*/
#define MIPS_INT_MASK_SPL_SOFT0 MIPS_SOFT_INT_MASK_0
#define MIPS_INT_MASK_SPL_SOFT1 (MIPS_SOFT_INT_MASK_1|MIPS_INT_MASK_SPL_SOFT0)
#define MIPS_INT_MASK_SPL0 (MIPS_INT_MASK_0|MIPS_INT_MASK_SPL_SOFT1)
#define MIPS_INT_MASK_SPL1 (MIPS_INT_MASK_1|MIPS_INT_MASK_SPL0)
#define MIPS_INT_MASK_SPL2 (MIPS_INT_MASK_2|MIPS_INT_MASK_SPL1)
#define MIPS_INT_MASK_SPL3 (MIPS_INT_MASK_3|MIPS_INT_MASK_SPL2)
#define MIPS_INT_MASK_SPL4 (MIPS_INT_MASK_4|MIPS_INT_MASK_SPL3)
#define MIPS_INT_MASK_SPL5 (MIPS_INT_MASK_5|MIPS_INT_MASK_SPL4)
/*
* mips3 CPUs have on-chip timer at INT_MASK_5. We don't support it yet.
*/