Commit Graph

360 Commits

Author SHA1 Message Date
lazymio
7dc858d03d
Add a test for arm privilege escalation 2022-01-04 20:30:07 +01:00
lazymio
cddc9cf2ed
Fix arm post init 2021-12-25 00:16:51 +01:00
lazymio
5b3a9e1024
Add test for arm v8 2021-12-24 23:45:57 +01:00
lazymio
4f73d75ea8
Fix #1500 2021-12-23 21:46:27 +01:00
lazymio
ef6f8a2427
Fix x86 CPUID 2021-12-22 23:39:41 +01:00
lazymio
7bb0abb977
Format 2021-12-22 20:37:15 +01:00
lazymio
7bb756249a
Better design of cpuid instruction hook 2021-12-22 20:36:56 +01:00
Quentin DUCASSE
033e79abac Added cache flush after code patching in unit tests for arm64 and riscv 2021-12-17 14:55:08 +01:00
Quentin DUCASSE
549274f44c Code patching tests for riscv and arm64 2021-12-10 15:27:54 +01:00
lazymio
8a0ca8715e
Fix SR read/write and a test 2021-12-04 23:22:28 +01:00
lazymio
221cde18df
Write CPSR as it is initiated from instructions to allow regs switch 2021-11-24 17:10:51 +01:00
lazymio
78e0ddbc4d
Fix mmio unmap 2021-11-24 00:18:19 +01:00
lazymio
4ed1c4cff9
Fix test name typo 2021-11-23 23:24:53 +01:00
Sven Bartscher
3e2580ef9e Add test case for #1497 2021-11-23 22:47:20 +01:00
lazymio
e11cc16e54
Implement high-resolution clock for mingw64 in test_ctl 2021-11-23 14:15:18 +01:00
lazymio
ccfb66611f
Move test to test_mem 2021-11-23 00:41:49 +01:00
Sven Bartscher
b35dbb90b2 Add test case for #1495 2021-11-22 18:48:16 +01:00
lazymio
907ec5095d
Fix a stackoverflow in tests 2021-11-21 19:28:45 +01:00
lazymio
fc467edbc6
Fix 32bit target getting wrong offset for mmio 2021-11-16 22:40:57 +01:00
lazymio
247ffbe0e8
Support nested uc_emu_start calls 2021-11-16 21:07:03 +01:00
lazymio
640251e1aa
Leave out size parameter in callback 2021-11-09 00:21:34 +01:00
lazymio
35017a614f
Slightly change UC_CTL_TB_REMOVE_CACHE 2021-11-08 22:09:33 +01:00
lazymio
e836b62e01
Minor fix for uc_ctl 2021-11-08 20:40:02 +01:00
lazymio
2f61592ff9
Fix uc_mem_protect 2021-11-07 20:37:58 +01:00
lazymio
c6fdbb3735
Add RISCV CSR registers 2021-11-07 20:36:04 +01:00
lazymio
01d7e454b7
Fix typo 2021-11-04 20:59:07 +01:00
lazymio
3aa2788586
Format 2021-11-04 18:39:52 +01:00
lazymio
dfbffa44ec
Support changing cpu model for ARM 2021-11-04 18:37:10 +01:00
lazymio
3e4b4af7d3
Support change page size 2021-11-04 17:03:30 +01:00
lazymio
67e2386da6
Add test and close #1477 2021-11-03 21:40:13 +01:00
lazymio
1a82248292
Add test for #992 2021-11-03 21:17:57 +01:00
lazymio
6b5529fcb7
Merge pull request #1458 from bet4it/patch
Port some patches from Unicorn1 to Unicorn2
2021-11-03 20:59:42 +01:00
lazymio
9818840f4e
Add tests for UC_HOOK_TCG_OPCODE 2021-11-03 20:56:45 +01:00
lazymio
58edb2abe7
Format 2021-11-03 13:28:12 +01:00
lazymio
09aa0f944f
Merge QDucasse:riscv_extension_d
Fix and close #1469

Fix test for riscv float points

Fix the riscv cpu config we left out
2021-11-03 13:20:46 +01:00
lazymio
eb75d459f0
Add a regression test for invalidating empty TB and have a better solution 2021-11-03 01:07:06 +01:00
Bet4
aaf340d9e4 Merge branch 'dev' into patch 2021-11-02 18:36:22 +08:00
lazymio
b7e82d460c
Expose more TB related stuff 2021-11-01 22:11:43 +01:00
lazymio
14e175394b
Fix Win32 time function for test_ctl 2021-11-01 19:43:30 +01:00
lazymio
9704618595
Fix test for Android due to clock() not working 2021-11-01 15:33:36 +01:00
lazymio
cee44b0464
Add tests and samples to show how to control TB cache 2021-11-01 14:46:01 +01:00
lazymio
fb45b287ba
Add multiple exits mechanism and tests&samples 2021-11-01 14:00:43 +01:00
lazymio
147cb62240
Add uc_close 2021-11-01 10:23:47 +01:00
lazymio
3dd2e0f95d
Basic implementation of uc_ctl 2021-11-01 00:39:36 +01:00
lazymio
84abf1d3a4
A stronger test and handle addr_end = 0 2021-10-31 21:01:55 +01:00
lazymio
4bcf1c4a7c
Flush TB at exit with a better approach instead of flushing tlb in uc1 2021-10-31 19:43:56 +01:00
lazymio
8e6f7e4fba
Add a regression test 2021-10-31 15:56:58 +01:00
lazymio
e62b0ef255
Add clang-format and format code to qemu code style 2021-10-29 12:44:49 +02:00
lazymio
9131856506
More tests 2021-10-26 11:32:57 +02:00
Aurimas Blažulionis
160045a910
Binary search mapped blocks 2021-10-20 20:49:55 +01:00