Add a test for arm privilege escalation
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@ -398,6 +398,52 @@ static void test_arm_thumb_smlabb()
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OK(uc_close(uc));
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}
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static void test_arm_not_allow_privilege_escalation()
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{
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uc_engine *uc;
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int r_cpsr, r_sp, r_spsr, r_lr;
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// E3C6601F : BIC r6, r6, #&1F
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// E3866013 : ORR r6, r6, #&13
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// E121F006 : MSR cpsr_c, r6 ; switch to SVC32 (should be ineffective
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// from USR32) E1A00000 : MOV r0,r0 EF000011 : SWI OS_Exit
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char code[] = "\x1f\x60\xc6\xe3\x13\x60\x86\xe3\x06\xf0\x21\xe1\x00\x00\xa0"
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"\xe1\x11\x00\x00\xef";
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uc_common_setup(&uc, UC_ARCH_ARM, UC_MODE_ARM, code, sizeof(code) - 1,
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UC_CPU_ARM_CORTEX_A9);
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// https://www.keil.com/pack/doc/CMSIS/Core_A/html/group__CMSIS__CPSR.html
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r_cpsr = 0x40000013; // SVC32
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OK(uc_reg_write(uc, UC_ARM_REG_CPSR, &r_cpsr));
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r_spsr = 0x40000013;
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OK(uc_reg_write(uc, UC_ARM_REG_SPSR, &r_spsr));
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r_sp = 0x12345678;
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OK(uc_reg_write(uc, UC_ARM_REG_SP, &r_sp));
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r_lr = 0x00102220;
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OK(uc_reg_write(uc, UC_ARM_REG_LR, &r_lr));
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r_cpsr = 0x40000010; // USR32
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OK(uc_reg_write(uc, UC_ARM_REG_CPSR, &r_cpsr));
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r_sp = 0x0010000;
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OK(uc_reg_write(uc, UC_ARM_REG_SP, &r_sp));
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r_lr = 0x0001234;
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OK(uc_reg_write(uc, UC_ARM_REG_LR, &r_lr));
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uc_assert_err(
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UC_ERR_EXCEPTION,
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uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
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OK(uc_reg_read(uc, UC_ARM_REG_CPSR, &r_cpsr));
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OK(uc_reg_read(uc, UC_ARM_REG_SP, &r_sp));
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OK(uc_reg_read(uc, UC_ARM_REG_LR, &r_lr));
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OK((r_cpsr & ((1 << 4) - 1)) == 0); // Stay in USR32
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OK(r_lr == 0x1234);
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OK(r_sp == 0x10000);
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OK(uc_close(uc));
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}
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TEST_LIST = {{"test_arm_nop", test_arm_nop},
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{"test_arm_thumb_sub", test_arm_thumb_sub},
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{"test_armeb_sub", test_armeb_sub},
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@ -410,4 +456,6 @@ TEST_LIST = {{"test_arm_nop", test_arm_nop},
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{"test_arm_usr32_to_svc32", test_arm_usr32_to_svc32},
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{"test_arm_v8", test_arm_v8},
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{"test_arm_thumb_smlabb", test_arm_thumb_smlabb},
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{"test_arm_not_allow_privilege_escalation",
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test_arm_not_allow_privilege_escalation},
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{NULL, NULL}};
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