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No more hard-coded cpu models

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This commit is contained in:
mio 2021-12-30 01:05:10 +01:00
parent cddc9cf2ed
commit 085ee07c73
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GPG Key ID: DFF27E34A47CB873
7 changed files with 16 additions and 16 deletions
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10
qemu/target/arm/cpu.c
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@ -2056,15 +2056,15 @@ ARMCPU *cpu_arm_init(struct uc_struct *uc)
#if !defined(TARGET_AARCH64)
if (uc->mode & UC_MODE_MCLASS) {
uc->cpu_model = 11;
uc->cpu_model = UC_CPU_ARM_CORTEX_M33;
} else if (uc->mode & UC_MODE_ARM926) {
uc->cpu_model = 0;
uc->cpu_model = UC_CPU_ARM_926;
} else if (uc->mode & UC_MODE_ARM946) {
uc->cpu_model = 1;
uc->cpu_model = UC_CPU_ARM_946;
} else if (uc->mode & UC_MODE_ARM1176) {
uc->cpu_model = 5;
uc->cpu_model = UC_CPU_ARM_1176;
} else if (uc->cpu_model == INT_MAX) {
uc->cpu_model = 17; // cortex-a15
uc->cpu_model = UC_CPU_ARM_CORTEX_A15; // cortex-a15
} else if (uc->cpu_model >= ARR_SIZE(arm_cpus)) {
free(cpu);
return NULL;

4
qemu/target/i386/cpu.c
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@ -5083,9 +5083,9 @@ X86CPU *cpu_x86_init(struct uc_struct *uc)
if (uc->cpu_model == INT_MAX) {
#ifdef TARGET_X86_64
uc->cpu_model = 0; // qemu64
uc->cpu_model = UC_CPU_X86_QEMU64; // qemu64
#else
uc->cpu_model = 4; // qemu32
uc->cpu_model = UC_CPU_X86_QEMU32; // qemu32
#endif
} else if (uc->cpu_model >= ARRAY_SIZE(builtin_x86_defs)) {
free(cpu);

2
qemu/target/m68k/cpu.c
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@ -271,7 +271,7 @@ M68kCPU *cpu_m68k_init(struct uc_struct *uc)
}
if (uc->cpu_model == INT_MAX) {
uc->cpu_model = 7; // cfv4e
uc->cpu_model = UC_CPU_M68K_CFV4E; // cfv4e
} else if (uc->cpu_model >= ARRAY_SIZE(m68k_cpus_type_infos)) {
free(cpu);
return NULL;

4
qemu/target/mips/cpu.c
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@ -164,14 +164,14 @@ MIPSCPU *cpu_mips_init(struct uc_struct *uc)
#ifdef TARGET_MIPS64
if (uc->cpu_model == INT_MAX) {
uc->cpu_model = 17; // R4000
uc->cpu_model = UC_CPU_MIPS64_R4000; // R4000
} else if (uc->cpu_model + UC_CPU_MIPS32_I7200 + 1 >= mips_defs_number ) {
free(cpu);
return NULL;
}
#else
if (uc->cpu_model == INT_MAX) {
uc->cpu_model = 10; // 74kf
uc->cpu_model = UC_CPU_MIPS32_74KF; // 74kf
} else if (uc->cpu_model >= mips_defs_number) {
free(cpu);
return NULL;

4
qemu/target/ppc/translate_init.inc.c
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@ -11149,14 +11149,14 @@ PowerPCCPU *cpu_ppc_init(struct uc_struct *uc)
memset(cpu, 0, sizeof(*cpu));
#ifdef TARGET_PPC64
if (uc->cpu_model == INT_MAX) {
uc->cpu_model = 18 + UC_CPU_PPC_7457A_V1_2 + 1; // power10_v1.0
uc->cpu_model = UC_CPU_PPC_POWER10_V1_0 + UC_CPU_PPC_7457A_V1_2 + 1; // power10_v1.0
} else if (uc->cpu_model + UC_CPU_PPC_7457A_V1_2 + 1 >= ARRAY_SIZE(ppc_cpus)) {
free(cpu);
return NULL;
}
#else
if (uc->cpu_model == INT_MAX) {
uc->cpu_model = 289; // 7457a_v1.2
uc->cpu_model = UC_CPU_PPC_7457A_V1_2; // 7457a_v1.2
} else if (uc->cpu_model >= ARRAY_SIZE(ppc_cpus)) {
free(cpu);
return NULL;

4
qemu/target/riscv/cpu.c
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@ -342,12 +342,12 @@ RISCVCPU *cpu_riscv_init(struct uc_struct *uc)
#ifdef TARGET_RISCV32
if (uc->cpu_model == INT_MAX) {
uc->cpu_model = 3;
uc->cpu_model = UC_CPU_RISCV32_SIFIVE_U34;
}
#else
/* TARGET_RISCV64 */
if (uc->cpu_model == INT_MAX) {
uc->cpu_model = 3;
uc->cpu_model = UC_CPU_RISCV64_SIFIVE_U54;
}
#endif

4
qemu/target/sparc/cpu.c
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@ -525,9 +525,9 @@ SPARCCPU *cpu_sparc_init(struct uc_struct *uc)
if (uc->cpu_model == INT_MAX) {
#ifdef TARGET_SPARC64
uc->cpu_model = 11; // Sun UltraSparc IV
uc->cpu_model = UC_CPU_SPARC64_SUN_ULTRASPARC_IV; // Sun UltraSparc IV
#else
uc->cpu_model = 12; // Leon 3
uc->cpu_model = UC_CPU_SPARC32_LEON3; // Leon 3
#endif
} else if (uc->cpu_model >= ARRAY_SIZE(sparc_defs)) {
free(cpu);