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2323 Commits

Author SHA1 Message Date
mio 3cbe32053b
Change git url to https url to avoid git submodule clone error 2022-01-18 21:09:01 +01:00
mio 218bddc0e0
Only use MAP_JIT on Apple Silicon 
MAP_JIT causes performance regression for fork()

See https://github.com/desktop/desktop/issues/12978
 2022-01-18 21:01:49 +01:00
mio c84dbac9a8
Rename build dir for python bindings 2022-01-18 20:15:28 +01:00
mio 0da1f02fde
Fix scale in tracing 2022-01-18 19:48:40 +01:00
mio 28e791a37f
Add debug tracing feature 
It's disabled by default, use -DUNICORN_TRACER=on to enable it
 2022-01-18 19:35:43 +01:00
lazymio abb958cac1
Merge pull request #1543 from bet4it/remove_hook 
rust: Allow to remove self inside a hook
 2022-01-18 10:45:03 +01:00
Bet4 5559c097d5 rust: Allow to remove self inside a hook 2022-01-17 21:56:33 +08:00
lazymio ea9c7425b0
Fix the wrong PC when arm translation fectches unmapped memory 
This behavior keeps the same with Unicorn1, though, different from arm doc
 2022-01-16 16:42:38 +01:00
lazymio 06be6fdc24
Merge pull request #1537 from gerph/clear-pending-hook-exception-before-emulation 
Clear Python pending hook exception before we enter the emulation.
 2022-01-15 22:13:24 +01:00
lazymio a5ceca6d51
Remove the static variable in flatviews_init 
Or we may get an invalid old (and free-ed) uc instance reference
 2022-01-15 22:11:14 +01:00
lazymio dfb0446137
Update bindings 2022-01-15 20:56:24 +01:00
Charles Ferguson 1ba59ed70a Clear Python pending hook exception before we enter the emulation. 
The pending exception hook is set when the hook raised an exception
and wants to report it outside the emulation loop. However, it is
never cleared back to None. This means that after an exception is
raised in a hook, all subsequent execution (even if successful) will
raise the exception.

This change clears the exception before we start another emulation,
which should ensure that if we have _hook_exception set, it really
is from hooks in this emulation run.
 2022-01-15 17:45:45 +00:00
lazymio 6ed2214399
Rebuilt hflags when swithing modes 
Or we may get the wrong mode during translation
 2022-01-14 19:37:48 +01:00
lazymio 36afa1022c
More PPC registers 
Add FPR0-31, CR0-7, LR, CTR, MSR, XER, FPSCR for PPC

Add a test for ppc32 float point
 2022-01-10 15:16:10 +01:00
lazymio be7fbf1306
Handle CPU fault when invalidating TB cache 2022-01-08 22:10:17 +01:00
lazymio c671efe798
Update bindings 2022-01-05 22:00:59 +01:00
lazymio 8ad9f8ecb1
This reverts Hack 05ba21160619724033ec83469bbb66bda9e3f5fb and applies the correct fix 
And enable experimental v8 support for arm max cpu
 2022-01-05 21:58:40 +01:00
lazymio 4567b4a790
Fix the wrong arm cpu index 2022-01-05 21:57:46 +01:00
lazymio e84a5c44e9
Add a test for arm mrc instruction (also for coproc) 2022-01-05 21:57:32 +01:00
lazymio 8e70f3e524
Format code 2022-01-05 21:56:58 +01:00
lazymio c3a49766d8
Fix #1522 2022-01-05 20:02:41 +01:00
lazymio b8817518ae
Add a test for arm64 pac extension 2022-01-05 20:02:21 +01:00
lazymio 7a886f59df
Fix #1525 2022-01-05 19:38:22 +01:00
lazymio 3f64491fda
Add further test for arm system mode transition 2022-01-05 19:38:02 +01:00
lazymio 6fabf30537
Fix a invalid memory access 
Note: This probably addresses the ramdom failed CI on mingw64
 2022-01-05 19:12:36 +01:00
lazymio c4b4189857
Update bindings 2022-01-04 21:12:52 +01:00
lazymio d854e22301
Add x87 FPU registers #1524 2022-01-04 21:12:12 +01:00
lazymio 47097b55b7
Fix #1520 2022-01-04 21:01:20 +01:00
lazymio 73149f3616
Fix test case 2022-01-04 20:54:52 +01:00
lazymio 7dc858d03d
Add a test for arm privilege escalation 2022-01-04 20:30:07 +01:00
mio 085ee07c73
No more hard-coded cpu models 2021-12-30 01:05:10 +01:00
lazymio cddc9cf2ed
Fix arm post init 2021-12-25 00:16:51 +01:00
lazymio 5b3a9e1024
Add test for arm v8 2021-12-24 23:45:57 +01:00
lazymio 4f73d75ea8
Fix #1500 2021-12-23 21:46:27 +01:00
lazymio ef6f8a2427
Fix x86 CPUID 2021-12-22 23:39:41 +01:00
lazymio 3184d3fcdf
Update python bindings 2021-12-22 20:46:14 +01:00
lazymio a81e155633
Pack test variables 2021-12-22 20:45:15 +01:00
lazymio 7bb0abb977
Format 2021-12-22 20:37:15 +01:00
lazymio 7bb756249a
Better design of cpuid instruction hook 2021-12-22 20:36:56 +01:00
lazymio dfb14e971f
Merge pull request #1512 from QDucasse/code_patching 
Issues with count for code patching
 2021-12-22 20:08:27 +01:00
Quentin DUCASSE 033e79abac Added cache flush after code patching in unit tests for arm64 and riscv 2021-12-17 14:55:08 +01:00
Quentin DUCASSE 549274f44c Code patching tests for riscv and arm64 2021-12-10 15:27:54 +01:00
lazymio 1923c12315
Merge pull request #1506 from zznop/1502-set-cpu-go 
SetCPUModel go binding for setting the CPU model
 2021-12-04 23:26:41 +01:00
lazymio 5eb5686538
Format 2021-12-04 23:22:42 +01:00
lazymio 8a0ca8715e
Fix SR read/write and a test 2021-12-04 23:22:28 +01:00
lazymio 3020d7b82a
Fix wrong m68k enums 2021-12-04 23:20:46 +01:00
Brandon Miller 2cc15c7260 Added SetCPUModel go binding 
Go cannot use C macros directly, so I followed existing convention and
added a helper to uc.c to call the uc_ctl_set_cpu_model macro
 2021-12-04 16:25:23 -05:00
Brandon Miller d204dc6374
Added SR to M68K reg_read and reg_write (#1507) 2021-12-02 14:12:49 +08:00
lazymio c190069b10
Merge pull request #1504 from Kritzefitz/rust-riscv-registers 
rust: Add RISCV CSR registers
 2021-12-01 13:28:13 +01:00
Sven Bartscher 59fb8a2733 rust: Add RISCV CSR registers 
The addition of these registers in the C base caused the rust values
for all floating point registers and the PC to point to some of the
CSR registers instead.
 2021-11-30 16:09:24 +01:00