Add further test for arm system mode transition
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@ -325,6 +325,8 @@ static void test_arm_usr32_to_svc32()
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OK(uc_reg_write(uc, UC_ARM_REG_CPSR, &r_cpsr));
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r_sp = 0x12345678;
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OK(uc_reg_write(uc, UC_ARM_REG_SP, &r_sp));
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r_lr = 0x00102220;
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OK(uc_reg_write(uc, UC_ARM_REG_LR, &r_lr));
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r_cpsr = 0x4000009b; // UND32
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OK(uc_reg_write(uc, UC_ARM_REG_CPSR, &r_cpsr));
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@ -332,18 +334,28 @@ static void test_arm_usr32_to_svc32()
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OK(uc_reg_write(uc, UC_ARM_REG_SPSR, &r_spsr));
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r_sp = 0xDEAD0000;
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OK(uc_reg_write(uc, UC_ARM_REG_SP, &r_sp));
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r_lr = code_start + 8;
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r_lr = 0x00509998;
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OK(uc_reg_write(uc, UC_ARM_REG_LR, &r_lr));
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OK(uc_reg_read(uc, UC_ARM_REG_CPSR, &r_cpsr));
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TEST_CHECK((r_cpsr & ((1 << 4) - 1)) == 0xb); // We are in UND32
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r_cpsr = 0x40000090; // USR32
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OK(uc_reg_write(uc, UC_ARM_REG_CPSR, &r_cpsr));
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r_sp = 0x0010000;
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OK(uc_reg_write(uc, UC_ARM_REG_R13, &r_sp));
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r_lr = 0x0001234;
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OK(uc_reg_write(uc, UC_ARM_REG_LR, &r_lr));
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OK(uc_reg_read(uc, UC_ARM_REG_CPSR, &r_cpsr));
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TEST_CHECK((r_cpsr & ((1 << 4) - 1)) == 0); // We are in USR32
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r_cpsr = 0x40000093; // SVC32
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OK(uc_reg_write(uc, UC_ARM_REG_CPSR, &r_cpsr));
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OK(uc_reg_read(uc, UC_ARM_REG_CPSR, &r_cpsr));
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OK(uc_reg_read(uc, UC_ARM_REG_SP, &r_sp));
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TEST_CHECK((r_cpsr & ((1 << 4) - 1)) == 3); // We are in SVC32
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TEST_CHECK(r_sp == 0x12345678);
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OK(uc_close(uc));
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