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2324 Commits

Author SHA1 Message Date
Alexander Graf
2827822ef1 S/390 fake TCG implementation 
Qemu won't let us run a KVM target without having host TCG support. Well, for
now we don't have any so let's implement a fake target that only stubs out
everything.

I tried to keep the patch as close to Uli's source as possible, so whenever
he feels like it he can easily diff his version against this one.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-12-05 17:36:00 +01:00
Aurelien Jarno
afa05235a5 tcg: initial mips support 
Based on a patch from Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>

A few words about design choices:
* Two registers, at and t0, are reserved for TCG internal use. They are
  useful for bswap and 64-bit ops.
* Most ops supports a constant argument with value 0, which is actually
  mapped to the zero register.
* While the at register is available for constant loading, ops only
  support a limited range of constants. TCG does a better job doing the
  register allocation and constant loading by itself. There are plenty of
  registers available anyway.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-12-01 00:06:15 +00:00
Aurelien Jarno
7d30175271 tcg: fix tcg_regset_{set,reset}_reg with more than 32 registers 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-11-24 19:51:13 +01:00
Aurelien Jarno
016b2b287d tcg/ppc64,x86_64: fix constraints of op_qemu_st64 
This op only takes two arguments, not two.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-11-24 19:51:12 +01:00
Magnus Damm
b785e4768b tcg/i386: remove duplicate sar opcode 
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-11-14 01:17:47 +01:00
Aurelien Jarno
6a957025eb tcg: improve output log 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-10-07 07:53:41 +02:00
Aurelien Jarno
94f4af02a1 tcg: allocate s->op_dead_iargs dynamically 
Similarly to what is already done in tcg_liveness_analysis() when
USE_LIVENESS_ANALYSIS is not set.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-10-04 15:30:44 +02:00
Aurelien Jarno
8389c67b82 tcg: remove dead code 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-10-04 15:16:46 +02:00
Aurelien Jarno
5f0ce17ffc tcg/i386: add support for ext{8,16}u_i32 TCG ops 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-10-04 13:24:45 +02:00
Aurelien Jarno
6458421802 tcg/x86_64: add support for ext{8,16,32}u_i{32,64} TCG ops 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-10-04 13:24:45 +02:00
Aurelien Jarno
cfc86988a8 tcg: add ext{8,16,32}u_i{32,64} TCG ops 
Currently zero extensions ops are implemented by a and op with a
constant. This is then catched in some backend, and replaced by
a zero extension instruction. While this works well on RISC
machines, this adds a useless register move on non-RISC machines.

Example on x86:
  ext16u_i32 r1, r2
is translated into
  mov    %eax,%ebx
  movzwl %bx, %ebx
while the optimized version should be:
  movzwl %ax, %ebx

This patch adds ext{8,16,32}u_i{32,64} TCG ops that can be
implemented in the backends to avoid emitting useless register
moves.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-10-04 13:24:45 +02:00
Aurelien Jarno
d68592022b Revert part of 6692b04319 
Committed by accident.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-09-30 14:16:12 +02:00
Aurelien Jarno
6692b04319 TCG: fix DEF2 macro 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-09-30 14:10:34 +02:00
Aurelien Jarno
17cf428f2e tcg/i386: generates dec/inc instead of sub/add when possible 
We must take care that dec/inc do not compute CF, which is needed by
add2/sub2.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-09-27 20:00:39 +02:00
Aurelien Jarno
b70650cbfe tcg/i386: optimize and $0xff(ff), reg 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-09-27 20:00:38 +02:00
Aurelien Jarno
a4b18c6ddb tcg/x86_64: generated dec/inc instead of sub/add when possible 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-09-27 18:08:16 +02:00
malc
d937032764 tcg/ppc: always use tcg_out_call 
Signed-off-by: malc <av1474@comtv.ru>
 2009-09-27 14:41:14 +04:00
Laurent Desnogues
7990496dcb ARM back-end: Use sxt[bh] instructions for ext{8, 6}s 
This patch uses sxtb for ext8s_i32 and sxth for ext16s_i32 in ARM back-end.

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-09-26 21:29:59 +02:00
Stefan Weil
d89c682f20 Suppress some variants of English in comments 
Replace surpress, supress by suppress.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-09-25 16:31:35 +02:00
Blue Swirl
96e132e24e Compile TCG runtime library only once 
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2009-09-20 19:06:34 +00:00
Stefan Weil
b348113d21 tcg: fix size of local variables in tcg_gen_bswap64_i64 
t0, t1 must be 64 bit values, not 32 bit.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-09-16 21:26:47 +02:00
malc
abb6ae2c00 X86_64: Use proper jumps/calls when displacement exceeds +-2G 
Signed-off-by: malc <av1474@comtv.ru>
 2009-09-11 01:38:52 +04:00
malc
c45851c44a When targeting PPU use rlwinm instead of andi. if possible 
andi. is microcoded and slow there.

Signed-off-by: malc <av1474@comtv.ru>
 2009-09-06 07:24:37 +04:00
Laurent Desnogues
4e6f6d4c20 ARM back-end: Fix encode_imm 
the encode_imm function in tcg/arm/tcg-target.c lacks shift declaration.

Laurent

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
 2009-08-25 01:14:14 +02:00
Laurent Desnogues
94953e6d74 ARM back-end: Handle all possible immediates for ALU ops 
this patch handles all possible constants for immediate operand of ALU ops.
I'm not very satisfied by the implementation.

Laurent

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
 2009-08-22 14:29:09 +02:00
Laurent Desnogues
f878d2d235 ARM back-end: Add TCG not 
this patch:

 - implements TCG not.

Laurent

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
 2009-08-22 13:55:06 +02:00
Juan Quintela
e2542fe2bc rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN 
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
 2009-07-27 14:09:21 -05:00
Juan Quintela
092c73eeff rename DEBUG_TCG to CONFIG_DEBUG_TCG 
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
 2009-07-27 14:09:21 -05:00
Juan Quintela
dfe5fff3ea change HOST_SOLARIS to CONFIG_SOLARIS{_VERSION} 
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
 2009-07-27 14:09:16 -05:00
Blue Swirl
871e6c3507 Fix CONFIG_PROFILER 
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2009-07-21 12:18:03 +00:00
malc
a71836de38 Fix rbase initialization 
Signed-off-by: malc <av1474@comtv.ru>
 2009-07-20 01:15:23 +04:00
Laurent Desnogues
cb4e581fae this patch improves the ARM back-end in the following way: 
- use movw/movt to load immediate values for ARMv7-A
- implement add/sub/and/or/xor with immediate (only 8-bit)

Laurent

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
 2009-07-18 14:20:30 +02:00
Aurelien Jarno
d9885a0b9e tcg: Fix tcg_gen_rotr_i64 
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-07-18 11:32:56 +02:00
malc
f6548c0a4b PPC 32/64 GUEST_BASE support 
Signed-off-by: malc <av1474@comtv.ru>
 2009-07-18 13:16:36 +04:00
malc
4f4a67ae78 Fix LHZX opcode value 
Signed-off-by: malc <av1474@comtv.ru>
 2009-07-18 13:16:13 +04:00
Juan Quintela
adea8197b4 Userspace guest address offsetting 
Fix type in i386 tcg.

Signed-off-by: Juan Quintela <quintela@redhat.com>
 2009-07-17 19:50:18 +01:00
Paul Brook
379f6698d7 Userspace guest address offsetting 
Re-implement GUEST_BASE support.
Offset guest ddress space by default if the guest binary contains
regions below the host mmap_min_addr.
Implement support for i386, x86-64 and arm hosts.

Signed-off-by: Riku Voipio <riku.voipio@iki.fi>
Signed-off-by: Paul Brook <paul@codesourcery.com>
 2009-07-17 13:12:41 +01:00
Paul Brook
2d69f3590d ARM host fixes 
Minor TCG cleanups and warning fixes for ARM hosts.

Signed-off-by: Paul Brook <paul@codesourcery.com>
 2009-07-17 11:21:12 +01:00
Paul Brook
5561650587 Include assert.h from qemu-common.h 
Include assert.h from qemu-common.h and remove other direct uses.
cpu-all.h still need to include it because of the dyngen-exec.h hacks

Signed-off-by: Paul Brook <paul@codesourcery.com>
 2009-05-13 20:54:26 +01:00
aurel32
cca8298291 tcg: make sure NDEBUG is defined before including <assert.h> 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7122 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-04-16 09:58:30 +00:00
aurel32
f839394688 Add a --enable-debug-tcg option to configure 
This patch allows DEBUG_TCGV to be defined (and also prevents NDEBUG
from being defined) when passing an option to the configure script.
This should help to prevent any accidental changes that enable
DEBUG_TCGV in tcg/tcg.h from being committed in future, and may
help to encourage testing with DEBUG_TCGV enabled.

Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7105 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-04-13 18:45:38 +00:00
malc
2ffebe2dcb Remove reserved registers from tcg_target_reg_alloc_order 
Noticed by Andreas Faerber

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7082 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-04-11 08:19:50 +00:00
malc
9de187a099 Whack [LS]MW 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7081 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-04-11 07:39:04 +00:00
malc
e23f2f36b1 Remove reserved registers from tcg_target_reg_alloc_order 
Noticed by Andreas Faerber

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7080 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-04-11 07:38:56 +00:00
aurel32
3e00b3f538 tcg/tcg.h: fix a few typos 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7024 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-04-07 19:57:24 +00:00
aurel32
b9c18f5658 tcg: add a CONST flag to TCG helpers 
A const function only reads its arguments and does not use TCG
globals variables. Hence a call to such a function does not
save TCG globals variabes back to their canonical location.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7008 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-04-06 12:33:59 +00:00
aurel32
34d5a9ff63 tcg: improve comment about pure functions 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7007 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-04-06 12:33:51 +00:00
aurel32
79d342dc6b tcg/x86_64: optimize register allocation order 
The beginning of the register allocation order list on the TCG x86_64
target matches the list of clobbered registers. This means that when an
helper is called, there is almost always clobbered registers that have
to be spilled.

The same way register %rsi and %rdi are at the top of the register
allocation order list, while they can't be used for load/store
operations. This means the data and/or address registers are very often
%rsi and %rdi, and their values have to be spilled, and then moved back
to another register.

This patches changes to the allocation order to avoid those effects.
It results in a 8% gain speed in qemu-x86_64 to compress a bzip2 file,
and a 6% gain in qemu-system-mips64 to compile a small application.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7003 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-04-05 20:08:50 +00:00
blueswir1
1da92db280 Fix branches and TLB matches for 64 bit targets 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6974 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-04-04 19:10:26 +00:00
blueswir1
f843e5282a Allocate space for static call args, increase stack frame size on Sparc64 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6973 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-04-04 15:33:03 +00:00
aurel32
864951afdd tcg: fix _tl aliases for divu/remu 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6948 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-29 14:08:54 +00:00
aurel32
ab36421e54 tcg: add _tl aliases for div/divu/rem/remu 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6939 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-29 01:19:22 +00:00
aurel32
604457d702 tcg/README: fix description of bswap32_i32/i64 
Thanks to Stuart Brady for the notice.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6920 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-28 23:27:30 +00:00
aurel32
86dbdd4012 tcg/x86_64: add bswap16_i{32,64} and bswap32_i64 ops 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6838 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-13 09:35:55 +00:00
aurel32
5d40cd6302 tcg/x86: add bswap16_i32 ops 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6837 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-13 09:35:49 +00:00
aurel32
4ad4ce16f4 tcg: update README wrt recent bswap changes 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6834 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-13 09:35:26 +00:00
aurel32
911d79bacf tcg: add _tl aliases to bswap16/32/64 TCG ops 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6833 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-13 09:35:19 +00:00
aurel32
9a5c57fdc1 tcg: add bswap16_i64 and bswap32_i64 TCG ops 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6832 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-13 09:35:12 +00:00
aurel32
dfa1a3f1c4 tcg: optimize tcg_gen_bswap16_i32 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6831 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-13 09:35:03 +00:00
aurel32
84aafb06ff tcg: allow bswap16_i32 to be implemented by TCG backends 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6830 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-13 09:34:56 +00:00
aurel32
66896cb803 tcg: rename bswap_i32/i64 functions 
Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-13 09:34:48 +00:00
aurel32
0dd0dd558b tcg: move {not,neg}_i{32,64} definitions at the right place 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6811 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-11 11:00:49 +00:00
aurel32
e5105083e6 tcg: fix commit r6805 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6810 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-11 02:57:30 +00:00
aurel32
419bafa517 tcg-arm: fix qemu_ld64 
Emulating fldl on arm doesn't seem to work too well. It's the way
qemu_ld64 is translated to arm instructions.

        tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
        tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, 4);

Consider case where data_reg==0, data_reg2==1, and addr_reg==0. First load
overwrited addr_reg. So let's put an if (data_ref==addr_reg).

(Pablo Virolainen)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6808 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-10 21:43:25 +00:00
aurel32
506bfcbb14 tcg: update TODO 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6807 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-10 19:37:56 +00:00
aurel32
9619376c1b tcg/x86: add not/neg/extu/bswap/rot i32 ops 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6806 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-10 19:37:46 +00:00
aurel32
7fc8105195 tcg: optimize logical operations 
Simplify nand/nor/eqv and move their optimizations to and/or/xor

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6805 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-10 19:37:39 +00:00
aurel32
43e860ef09 Fix tcg after commit 6800 
The introduction of TCGV_EQUAL and not op is slightly broken.
The definition of DEBUG_TCGV shows that.

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6802 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-10 10:29:45 +00:00
aurel32
fe75bcf70d tcg: use TCGV_EQUAL_I{32,64} 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6800 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-10 08:57:16 +00:00
aurel32
44e6acb017 tcg: define TCGV_EQUAL_I{32,64} 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6799 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-10 08:56:30 +00:00
aurel32
c29d0de4d6 tcg: optimize nor(X, Y, Y), used on PPC for not(X, Y) 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6798 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-09 22:35:22 +00:00
aurel32
d2604285b2 Implement TCG not ops for x86-64 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6797 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-09 22:35:13 +00:00
aurel32
f31e937064 tcg: don't define TCG rotation ops if they are not supported 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6796 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-09 21:58:46 +00:00
aurel32
d42f183c04 Implement TCG rotation ops for x86-64 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6795 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-09 18:50:53 +00:00
blueswir1
e63d7abdde Prune unused TCG_AREGs 
Remove definitions for TCG_AREGs corresponding to AREG definitions
removed in r6778.

Signed-off-by: Stuart Brady <stuart.brady@gmail.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6779 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-08 14:45:45 +00:00
blueswir1
9e622b15a3 Sparse fixes: truncation by cast 
Fix Sparse warnings about constant truncation caused by cast


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6737 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-07 15:46:23 +00:00
blueswir1
9c22bc6312 TCG: remove obsolete old_op_count profiler field 
Since we don't generate any "old op" anymore, the old_op_count
is unneeded.

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6614 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-02-11 19:47:39 +00:00
malc
095271d4ea Add missing r24..r26 to callee save registers 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6613 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-02-11 18:54:02 +00:00
malc
eb2eb1dc00 Add missing r24..r26 to calle save registers 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6612 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-02-11 18:51:19 +00:00
blueswir1
2edd089f8a Add "static" 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6588 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-02-10 19:00:31 +00:00
aurel32
a747723bed Fix DEBUG_TCGV compile error. 
Don't call TCGV_LOW on arg2.  This section of code falls under

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6585 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-02-09 20:43:53 +00:00
malc
5db3ee7991 R13 is reserved for small data area pointer by SVR4 PPC ABI 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6450 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-26 18:21:53 +00:00
aliguori
8fec2b8c45 global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost) 
These are references to 'loglevel' that aren't on a simple 'if (loglevel &
X) qemu_log()' statement.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6340 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-15 22:36:53 +00:00
aliguori
93fcfe39a0 Convert references to logfile/loglevel to use qemu_log*() macros 
This is a large patch that changes all occurrences of logfile/loglevel
global variables to use the new qemu_log*() macros.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6338 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-15 22:34:14 +00:00
malc
e58ffeb322 Remove all traces of __powerpc__ 
According to $GCC/gcc/config/rs6000/rs6000-c.c _ARCH_PPC is the
ubiquitous define which should be used to test whether gcc targets
PowerPC, on 64bit platforms _ARCH_PPC64 will be also defined.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6301 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-14 18:39:49 +00:00
aurel32
5d04f23bdf tcg: remove tcg_global_reg2_new_hack() 
This patch removes the unused tcg_global_reg2_new_hack() function, which
was added in r4438 to work around a register shortage problem regarding
dyngen.  The only ever user of this function was removed in r4577.

Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6150 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-03 12:36:05 +00:00
aurel32
f53bca180a TCG: Fix documentation of qemu_ld/st ops 
The functions defined in tcg/tcg-op.h have no _i32 or _i64 suffix,
qemu_ld64 and qemu_st64 were missing from the list, and there are
no 'plain' qemu_ld/qemu_st ops.

Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6148 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-03 12:35:47 +00:00
aurel32
df9247b264 tcg_temp_local_new should take no parameter 
This patch removes useless type information in some calls to
tcg_temp_local_new.  It also removes the parameter from the
macro declaration;  if a target has to use a specific non-default
size then it should use tcg_temp_local_new_{i32,i64}.

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6146 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-01 14:09:05 +00:00
malc
b1503cda1e Use the ARRAY_SIZE() macro where appropriate. 
Change from v1:
  Avoid changing the existing coding style in certain files.

Signed-off-by: Stuart Brady <stuart.brady@gmail.com>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-22 20:33:55 +00:00
aurel32
3e9a474e3d tcg: kill two warnings 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6029 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-14 17:29:58 +00:00
aurel32
9db3ba4db2 TCG x86/x86-64: use move with zero-extend for loads/stores 
Starting with version 4.3, gcc returns the result of a function in
rax/eax/ax/al instead of rax/eax, depending of the return type. As
a consequence we should use a zero extend moe in TCG loads/stores.

See http://gcc.gnu.org/ml/gcc/2008-01/msg00052.html for more details.

A big thanks to malc who founds the problem and wrote the x86 patch.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6011 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-13 18:57:21 +00:00
blueswir1
1d6198c3b0 Remove unnecessary trailing newlines 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6000 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-13 09:32:43 +00:00
blueswir1
7a3a514140 Fix TARGET_LONG_BITS warning in TCG 
Looking at tcg/tcg.c:828, the bug that the warning indicated would show up as
incorrect PC shown in log, only on 32 bit big endian host emulating a 64 bit
target, -d op flag enabled. Now that dyngen is gone, the patch can be applied.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5998 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-13 08:16:43 +00:00
malc
902b3d5c39 Introduce and use cache-utils.[ch] 
Thanks to Segher Boessenkool and Holis Blanchard.

AIX and Darwin cache inquiry:
http://gcc.gnu.org/ml/gcc-patches/2007-08/msg00388.html

Auxiliary vectors:
http://manugarg.googlepages.com/aboutelfauxiliaryvectors

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5973 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-10 19:18:40 +00:00
balrog
aef3a282a4 Fix 64-bit targets compilation on ARM host. 
Only fix compilation, probably doesn't run.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5947 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-07 23:35:47 +00:00
aurel32
54604f74ae Some cleanups after dyngen removal 
1. hostregs_helper.h: fix comment
2. translate-all.c: rename dyngen_code(_search_pc) to
   tcg_gen_code(_search_pc)
3. tcg.c:
  - rename dyngen_table_op_count to tcg_table_op_count
  - no need to generate a log of dyngen ops generated
  - rename dyngen_code(_search_pc) to tcg_gen_code(_search_pc)
4. tcg.h: rename dyngen_code(_search_pc) to
   tcg_gen_code(_search_pc)

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5936 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-07 20:35:00 +00:00
aurel32
49516bc0d6 Some cleanups after dyngen removal 
this patch removes some now unused things after dyngen removal.

1. dyngen-exec.h:  op_param, op _jmp and some associated macros
   are now unused;
2. Makefile.target:  tcg-dyngen is not needed anymore
2. tcg/tcg-op.h, tcg/tcg-opc.h:  gen-op.h is dead
3. tcg.c:
    - INDEX_op_end is now the first op
    - CONFIG_DYNGEN_OP is never defined
4. tcg.h:  dyngen_op not needed anymore
5. exec-all.h:  remove some ASM macros.

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5922 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-07 18:15:45 +00:00
blueswir1
a810a2de17 Some fixes for TCG debugging 
This fixes a few things after Paul's improvements for TCG debugging:

  - change TCGv_i64 field name to something different from
    TCGv_i32
  - fix things in tcg that the above change made visible.

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5919 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-07 17:16:42 +00:00
aurel32
86e840eef7 Remove a few dyngen and dyngen related code 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5914 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-07 15:21:23 +00:00
balrog
0c9c3a9e3a arm: Don't potentially overwrite input registers in add2, sub2. 
According to malc TCG will often genereate an add2/sub2/mul2 with low
half of the output in the same register as high half of one of the
inputs, so account for that.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5847 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-01 11:57:21 +00:00
balrog
fe33867b0d Don't rely on ARM tcg_out_goto() generating just a single insn. 
Otherwise when tb_exit generates a jump beyond the pc-relative range,
tcg_out_goto() spans two/three instructions and we load the tb return
value from a wrong address.  This is #ifdefed out currently because
we take care for the jumps to be local.
Problem spotted by Steffen Liebergeld.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5845 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-01 02:17:12 +00:00
balrog
3233f0d463 Use libgcc __clear_cache to clean icache, when available. 
Calling the clear cache syscall directly generates an illegal instruction 
on some (armv4) kernels.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5843 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-01 02:02:37 +00:00
malc
ebd486d593 Fix alignment of 64bit args 
Unbreaks sparc and mips64el. (Reported by Thiemo Seufer)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5815 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-29 19:55:15 +00:00
malc
b29fe3ed48 Preliminary AIX support 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5732 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-18 01:42:22 +00:00
pbrook
a7812ae412 TCG variable type checking. 
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-17 14:43:54 +00:00
malc
2946898b48 Rename misnamed BACK_CHAIN_OFFSET to LR_OFFSET 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5711 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-12 20:36:24 +00:00
malc
8421d9e56f Avoid compiler warning 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5710 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-12 20:36:21 +00:00
malc
828808f5ec Fix alignment problem with some 64bit load/store instructions 
LD/STD/LWA require displacement to be multiple of 4, provide
tcg_out_ldsta which checks the supplied displacement and falls
back on indexed variant when the check fails. All uses of
LD/STD/LWA outside of tcg_out_ldst appear to be safe.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5670 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-11 03:04:57 +00:00
pbrook
0c5f3c8d7d Mention output overlaps. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5619 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-04 13:17:17 +00:00
pbrook
de3526b2b3 Fix rotri_i64 typo. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5609 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-03 13:30:50 +00:00
aurel32
158245714e tcg-ops.h: add rotl/rotli and rotr/rotri TCG instructions 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5607 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-03 07:08:36 +00:00
aurel32
f02bb954a5 tcg-op.h: reorder _i64 instructions common to 32- and 64-bit targets 
Use the same order as the _i32 version (pure code move). Suggested by
Laurent Laurent Desnogues.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5606 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-03 07:08:26 +00:00
pbrook
10460c8ac4 64-bit target subfi fix. 
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5602 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-02 13:26:16 +00:00
aurel32
0045734ab7 tcg-ops.h: add a subfi wrapper 
Add a subfi (subtract from immediate) wrapper, useful for the PPC target.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5599 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-02 08:23:04 +00:00
aurel32
6359706f93 tcg-ops.h: _i64 TCG immediate instructions cleanup 
Move addi_i64, muli_i64 and subi_i64 out of #if TCG_TARGET_REG_BITS
as both implementations are strictly identical. Use the same
optimisation (ie when imm == 0) for addi_i64 and subi_64 than the
32-bit version.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5598 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-02 08:22:54 +00:00
blueswir1
b1d8e52e63 Fix undeclared symbol warnings from sparse 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5539 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-26 13:43:07 +00:00
aurel32
bdffd4a9d7 TCG: add tcg_const_local_tl() 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5504 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-21 11:30:45 +00:00
aurel32
f24cb33e5e TCG: add logical operations found on alpha and powerpc processors 
- andc_i32/i64 t0, t1, t2
- eqv_i32/i64 t0, t1, t2
- nand_i32/i64 t0, t1, t2
- nor_i32/i64 t0, t1, t2
- orc_i32/i64 t0, t1, t2

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5501 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-21 11:28:59 +00:00
blueswir1
d4a9eb1fc6 Add some missing static and const qualifiers, reg_names only used if NDEBUG set 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5421 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-05 09:59:14 +00:00
malc
3ee1b8550c Optimize 64 bit bswap 
Use rldimi instead of rldicr/or pair, saves us one instruction.
Suggested by Hollis Blanchard.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5404 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-02 20:02:31 +00:00
pbrook
88422e2ebd Fix tcg_gen_concat32_i64 on 64-bit hosts. 
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5306 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-23 22:31:10 +00:00
malc
f8edcbaa2d Avoid clobbering input register in qemu_ld64+bswap+useronly case 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5287 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-22 01:08:08 +00:00
blueswir1
945ca823b9 Add concat32_i64 and concat_tl_i64 ops 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5282 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-21 18:32:28 +00:00
pbrook
36aa55dcd9 Add concat_i32_i64 op. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5280 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-21 13:48:32 +00:00
blueswir1
f48f3ede71 Display TCGCond name in tcg dumper (original patch by Tristan Gingold) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5208 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-14 07:45:17 +00:00
blueswir1
9d0efc88e4 Use 64 bit loads for tlb addend only if addend size is 64 bits 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5203 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-13 20:07:53 +00:00
blueswir1
baf8cc5275 Fix stack alignment on Sparc32 host 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5202 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-13 20:05:32 +00:00
pbrook
733fef0e40 TCG: Use x86-64 zero extension instructions. 
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5180 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-07 18:07:39 +00:00
pbrook
b6d17150af Implement TCG sign extension ops for x86-64. 
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5179 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-07 17:45:15 +00:00
aurel32
00dbbb03b6 Revert "TCG: enable debug" 
This reverts commit 5166, commited by error.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5169 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-05 14:22:24 +00:00
aurel32
b24a39fab0 TCG: enable debug 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5166 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-05 14:19:35 +00:00
blueswir1
79383c9c08 Fix some warnings that would be generated by gcc -Wredundant-decls 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-30 09:51:20 +00:00
malc
70fa887c14 Relax qemu_ld/st constraints for !SOFTMMU case 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5038 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-21 01:14:07 +00:00
malc
735ee40d92 Relax qemu_ld/st constraints for !SOFTMMU case 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5034 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-20 22:39:22 +00:00
malc
109719ec9e Avoid clobbering input/aliased registers in !SOFTMMU+64bit+bswap case 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5033 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-20 22:39:19 +00:00
malc
0b7c1d897f Clear the upper 32 bits of addr_reg in TARGET_LONG_BITS == 32 case 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5032 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-20 22:39:17 +00:00
malc
a2a546b3fc Move tcg_out_tlb_read into #ifdef CONFIG_SOFTMMU block to avoid compiler warning 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5031 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-20 22:39:14 +00:00
blueswir1
8fcd36920e Fix some warnings that would be generated by gcc -Wmissing-prototypes 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5022 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-17 20:26:25 +00:00
blueswir1
6f41b7772d Fix 64 bit constant generation 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5020 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-17 20:14:16 +00:00
blueswir1
90cbed4656 Fix 32 bit address overflow 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5019 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-17 16:13:02 +00:00
blueswir1
bffe143153 Restore AREG0 after calls 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5018 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-17 14:34:27 +00:00
blueswir1
56fc64dfd0 Sparc code generator update (fix qemu_ld & qemu_st) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5014 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-16 19:54:01 +00:00
blueswir1
53c3748794 Sparc code generator update 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5009 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-15 18:14:44 +00:00
malc
bf6bca527c Account for MacOS X ABI reserved space in linkage area (Andreas Faerber) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4985 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-03 19:04:11 +00:00
malc
f9bf298717 Preliminary MacOS X on PPC32 support 
Big thanks to BlueSwirl for Sparc failure analysis.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4984 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-03 19:04:07 +00:00
malc
52781543ad On ppc32 make tb_set_jmp_target1 behave like it does on a ppc64 
Avoids nasty warnings about flush_icache_range from gcc4 and inability
to compile [cpu-]exec.c with gcc3 and -O, also the function is much
too large to be candidate for inlining anyway.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4974 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-29 20:08:17 +00:00
malc
fe6f943f3b Immediate versions of some operations 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4962 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-28 23:46:06 +00:00
malc
000a2d866a Do not try handle "special" arguments of and/or/xor/shl/shr, upper level does it 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4961 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-28 23:46:03 +00:00
malc
e924bbec7a Set the L field of CMP[L][I] when dealing with 64 bit quantities 
This (along with previous 2 commits) makes X86_64 work on ppc64 too.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4960 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-28 19:42:23 +00:00
malc
880e52b8b0 Fix preprocessor guard condition 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4959 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-28 19:42:20 +00:00
malc
95153fde07 Remove leftover from previous way to load 64 bit constants 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4958 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-28 19:42:17 +00:00
malc
4a40e23194 Special-case some paths inside tcg_out_tlb_read 
a. Use 32bit arithmetics in TARGET_LONG_BITS == 32 case
b. Optimize byte access case in TARGET_LONG_BITS == 64 case

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4955 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-27 11:09:21 +00:00
malc
301f6d903a Fix the opcode value of LWA 
That should teach one to not blindly trust documentation that will
(out of the blue) use decimal and binary representation for numbers in
the same chart for no apparent reason and without any prefixes, sigh..

Unbreaks MIPS.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4954 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-27 10:28:15 +00:00
blueswir1
e97b640d47 Try to avoid glibc global register mangling, again 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4953 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-26 17:19:35 +00:00
malc
c070355d39 Relax memory operations constraints 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4950 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-26 11:21:03 +00:00
malc
b01d9fea6c Fix qemu_ld64 constraint list 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4949 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-26 11:21:00 +00:00
malc
e03ae7f9b3 Use proper offset for LR save slot 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4948 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-26 11:20:57 +00:00
malc
5424fd1018 Reduce amount of space reserved for tb jump 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4947 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-26 11:20:54 +00:00
malc
6fc9dbcc17 Fix and improve 64 bit immediate loading 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4946 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-26 11:20:50 +00:00
malc
450e62e768 Fix EXTSW arguments 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4945 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-26 11:20:44 +00:00
malc
e7d05e6f1d Use proper value for TCG_TARGET_CALL_STACK_OFFSET 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4941 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-24 22:56:21 +00:00
malc
a69abbe0b3 Emit and use adhoc function descriptor for code_gen_prologue on PPC64 
Thus avoiding fragile inline assembly hackery to call into generated
code.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4939 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-24 17:37:09 +00:00
malc
6926be2a59 Remove neg_i32 debugging leftover 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4935 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-23 20:01:27 +00:00
malc
e46b9681e5 Provide extNs_M instructions 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4934 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-23 20:01:23 +00:00
malc
1d58ee9f3b Remove stray "i" from mul_i64 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4933 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-23 20:01:19 +00:00
malc
810260a8f3 Preliminary PPC64/Linux host support 
ppc64.ld from Heikki Lindholm's patch
http://marc.info/?l=qemu-devel&m=114086179024634&w=2

Issues:
x86_64 tripple faults shortly after decompressing the kernel
No immediate versions of most 64 bit operations
More...

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4932 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-23 19:17:46 +00:00
bellard
d643ccca01 64 bit signed comparison fix (Juergen Lock) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4855 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-07 20:15:54 +00:00
blueswir1
d795eb86d7 Fix 64 bit constant generation 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4854 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-07 19:34:45 +00:00
malc
e924c48573 Fuse EQ and NE handling in tcg_out_brcond2 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4845 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-03 23:49:14 +00:00
malc
8c5e95d807 Mask LL portion of B to 24 bits in tcg_out_b (Thanks to Thiemo Seufer) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4841 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-03 18:51:23 +00:00
pbrook
a50f5b9186 Suppress bogus compiler warnings. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4803 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-29 15:25:29 +00:00
malc
ca88500f43 According to gcc-4.3.0/gcc/config/rs6000/crtsavres.asm R13 is volatile 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4779 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-23 05:47:06 +00:00
malc
a35e86c55f Shuffle contents of tcg_target_reg_alloc_order 
Move reserved/volatile registers down. Currently qemu_ld/stXX are
marked with TCG_OPF_CALL_CLOBBER and since memory accesses are
frequent and R3 through R12 are volatile moving this down results in
less spills and tighter generated code.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4778 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-23 05:47:03 +00:00
malc
17ca26e791 Save LR into proper place on callers stack frame 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4745 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-18 01:58:52 +00:00
malc
c596defdb9 Reimplement brcond2 and refactor brcond 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4738 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-12 12:33:10 +00:00
ths
8df1ca4ba5 Allocate register pair for 64-bit registers on 32-bit host. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4730 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-11 11:03:34 +00:00
malc
0d5bd3631f Remove stray variable 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4725 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-10 01:47:17 +00:00
malc
77b73de676 Use rem/div[u]_i32 drop div[u]2_i32 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4722 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-09 23:44:44 +00:00
malc
fa4fbfb98a Emit trampolines manually in prologue 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4715 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-09 19:57:36 +00:00
malc
5d794885a2 Fix test for signed div fast path 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4714 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-09 19:57:27 +00:00
malc
398ce98e4f Fix div[u]2. 
Previous code assummed 32 by 32 bit divmod operation, and survived
x86_64 test only by sheer luck. MIPS wasn't so forgiving.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4705 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-09 06:06:25 +00:00
malc
0a878c4760 PPC TCG Fixes 
* Fix typo in aliased div2
* "Optimize" aliased div2/divu2
* Fix two remaining branch retranslation problems
  (Kudos to Andrzej Zaborowski)
* Rework goto_tb and set_jmp_target1
* Use correct size when flushing icache
* Use correct register selection for ORI
  (Was harmless since in both cases srcreg was equal to dstreg)



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4691 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-07 20:31:33 +00:00
ths
c588979bfc Allocate a register pair instead of a single register. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4688 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-07 04:31:49 +00:00
ths
1235fc066a Spelling fixes, by Stefan Weil. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4655 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-03 19:51:57 +00:00
bellard
932a690969 support of long calls for PPC (malc) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4629 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-30 20:56:52 +00:00
bellard
f3f478a7ef Fix signed/unsigned issues of immediate version of brcond (malc) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4588 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-26 19:11:07 +00:00
bellard
2662e13f68 ppc TCG target (malc) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4584 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-25 18:59:57 +00:00
bellard
560f92cc34 jump simplification 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4583 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-25 18:49:06 +00:00
bellard
affa3264db jump optimizations 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4582 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-25 18:41:58 +00:00
bellard
0a6b7b7813 update 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4581 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-25 18:24:40 +00:00
bellard
b314f2706b suppressed unused macro handling 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4580 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-25 18:21:31 +00:00
bellard
641d5fbe6b added local temporaries 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4576 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-25 17:24:00 +00:00
blueswir1
8384dd67fe Implement byte swapping accesses 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4574 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-25 11:19:24 +00:00
pbrook
9b7b85d260 Fix off-by-one unwinding error. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4570 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-25 00:36:06 +00:00
balrog
d0660ed482 Relax a constraint for qemu_ld64 on ARM host. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4567 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-24 23:12:19 +00:00
balrog
eae6ce5238 Fix a deadly typo, correct comments. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4566 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-24 22:56:51 +00:00
pbrook
3979144c49 Fix ARM host TLB. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4564 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-24 20:07:07 +00:00
blueswir1
b101234a8e Implement 64-bit constant loads 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4561 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-24 18:09:50 +00:00
blueswir1
26cc915cff Use sethi and arith functions, fix comment 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4560 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-24 18:06:35 +00:00
blueswir1
77fcd0934a Fix stack offsets and alignment 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4559 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-24 16:41:17 +00:00
blueswir1
64e3257c03 Define stack offsets 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4554 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-24 05:36:16 +00:00
pbrook
bcb0126ff4 More TCGv type fixes. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4553 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-24 02:24:25 +00:00
pbrook
cb63669a54 Fix ARM conditional branch bug. 
Add tcg_gen_brcondi.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4552 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-24 02:22:00 +00:00
balrog
91a3c1b00d Comment non-obvious calculation. Don't clobber r3 in qemu_st64. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4548 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-23 18:51:15 +00:00
balrog
e936243aca A branch insn must not overwrite the branch target before relocation. 
When a branch to label is translated it generates a reloc that is filled in
when the label is translated.  However, when handling an exception and
searching for the pc we abort the translation early and we sometimes
translate the branch but not the corresponding label and so no relocation
is done.  When the block is executed again the branch points to no-where.

It seems tcg/sparc/ is going to suffer from the same issue.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4547 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-23 18:50:44 +00:00
bellard
e8996ee012 added tcg_temp_free() and improved the handling of constants 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4544 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-23 17:33:39 +00:00
balrog
225b437649 Fix qemu_ld/st for mem_index > 0 on arm host. 
offsetof(CPUState, tlb_table[mem_index][0].addr_read) with mem_index > 0
was larger than max immediate offset for ldr and str (12-bit) so insert an
additional insn to add the mem_index offset.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4542 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-23 12:55:11 +00:00
balrog
bedba0cd07 Define TCG_TARGET_CALL_STACK_OFFSET on arm. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4541 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-23 12:47:22 +00:00
bellard
24bf7b3a1d compilation fix 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4540 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-23 11:58:32 +00:00
bellard
a23a9ec615 profiler clean up 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4537 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-23 09:52:20 +00:00
bellard
7e4597d7ae added debug_insn_start debug instruction 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4531 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-22 16:56:05 +00:00
bellard
4dc81f2822 debug output: write helper names 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4529 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-22 16:08:32 +00:00
bellard
39cf05d322 more generic call codegen 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4528 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-22 14:59:57 +00:00
bellard
cf60bce405 fixed zero shifts (64 bit case) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4527 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-22 14:39:25 +00:00
bellard
34151a20ea small shift opts 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4525 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-22 13:25:14 +00:00
bellard
e5097dc8e3 fixed dead global variable update 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4512 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-21 16:24:20 +00:00
balrog
204c1674ef Fix 8-bit signed load/store and a typo. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4504 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-20 11:28:35 +00:00
balrog
650bbb361e Implement neg_i32, clean-up. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4503 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-20 11:26:40 +00:00
balrog
a2a64a1f2d Remove dyngen ARM code, which did't build. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4501 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-20 00:01:55 +00:00
balrog
811d4cf4b0 ARM host support for TCG targets. 
Updated from previous version to use the tcg prologue/epilogue mechanism, may be slower than direct call.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4500 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-19 23:59:38 +00:00
blueswir1
c44f945a92 Better solution for the alignment problem 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4498 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-19 16:32:18 +00:00
ths
48d38ca52b Switch most MIPS logical and arithmetic instructions to TCG. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4496 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-18 22:50:49 +00:00
blueswir1
57e49b4074 Fix constant checks on Sparc64 host 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4486 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-18 08:11:14 +00:00
blueswir1
d4929d58a1 Fix TCG alignment problems on Sparc64 host 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4485 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-18 07:49:05 +00:00
bellard
c6e113f568 added 'pure' function attribute - fixed indirect function calls 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4469 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-17 12:42:15 +00:00
bellard
0b6ce4cffe added not pseudo op - more _tl macros 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4468 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-17 12:40:44 +00:00
blueswir1
9a7f32283c Fix qemu_ld/st branches, constification, use orcc for tst synthetic op 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4466 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-17 09:41:14 +00:00
blueswir1
f5ef6aacd4 Implement qemu_ld/st, fix brcond, handle more corner cases 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4463 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-16 20:15:58 +00:00
blueswir1
cf7c2ca5ff Implement brcond, ldst with large offset; fix direct jump, prologue 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4461 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-15 19:44:09 +00:00
blueswir1
f02ca5cbea Fix bit fitting checks 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4460 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-15 17:30:17 +00:00
blueswir1
7d55170268 Fix compilation on Sparc host, implement ld and st 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4457 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-14 19:22:05 +00:00
bellard
6a8d7b7637 temporary hack to handle register shortage with dyngen for qemu_st64() 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4438 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-12 13:49:14 +00:00
pbrook
390efc54fb Add TCG native negation op. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4426 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-11 14:35:37 +00:00
pbrook
868314358e Add zero extension (pseudo-)ops. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4424 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-11 12:22:01 +00:00
bellard
3375984648 REXB optimization cannot be done at this level 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4420 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-10 21:58:28 +00:00
bellard
3c3a1d200c fixed qemu_st8 insn - prologue saved too many registers 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4418 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-10 21:42:05 +00:00
pbrook
9815642347 Fix DEBUG_TCGV. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4415 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-10 18:43:02 +00:00
blueswir1
bf6247fb76 Rename CONFIG_NO_DYNGEN_OP to CONFIG_DYNGEN_OP to avoid double negatives 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4412 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-10 12:27:33 +00:00
bellard
b03cce8e08 fixed global variable handling with qemu load/stores - initial global prologue/epilogue implementation 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4406 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-10 10:52:05 +00:00
balrog
c7b76a0ae3 Fix i64 remainder calculation copy-paste error. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4357 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-06 14:40:28 +00:00
ths
f730fd27b8 Add helpers and shorthands for mul and muli operations. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4319 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-04 08:14:08 +00:00
blueswir1
4d07272d80 Skip register moves when the target and the source are the same 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4312 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-03 20:52:26 +00:00
aurel32
f54b3f920f HPPA (PA-RISC) host support 
(Stuart Brady)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4199 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-12 20:14:54 +00:00
aurel32
ca10f86763 Remove osdep.c/qemu-img code duplication 
(Kevin Wolf)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4191 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-11 21:35:42 +00:00
pbrook
b010980544 ARM TCG conversion 9/16. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4146 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-31 03:47:03 +00:00
pbrook
6ddbc6e4cf ARM TCG conversion 7/16. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4144 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-31 03:46:33 +00:00
blueswir1
e429073d4e Add TL variants of trunc and ext/extu 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4099 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-22 08:39:04 +00:00
blueswir1
cf2be98437 Prepare for op.c removal and zero legacy ops 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4095 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-21 18:03:09 +00:00
blueswir1
fb50d4134d Make TCG br op available 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4093 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-21 17:58:45 +00:00
blueswir1
c4071c9014 Increase max temps limit 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4074 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-16 19:21:07 +00:00
blueswir1
a768e4b25a Add discard_ptr and discard_tl 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4072 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-16 19:16:37 +00:00
blueswir1
a98824ac42 Add tcg_const_tl 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4053 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-13 20:46:42 +00:00
blueswir1
e4d5434c3a Fix i32 memory backed variables on 64-bit host 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4044 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-13 17:34:19 +00:00
aurel32
5e85404a56 TCG README fixes (Stuart Brady) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4042 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-12 21:40:02 +00:00
blueswir1
0954d0d9e2 Remove blank elements in tcg_target_reg_alloc_order[] (Stuart Brady) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4039 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-11 21:01:02 +00:00
blueswir1
b3db875812 Add function prologue, fix pointer load on Sparc64 host 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4027 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-08 13:33:42 +00:00
blueswir1
53cd927312 Update based on Stuart Brady's comments 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4026 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-07 18:21:39 +00:00
pbrook
21fc3cfc10 32-bit host sign extension fix (Juergen Lock). 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4017 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-04 23:52:47 +00:00
blueswir1
0cf767d663 Add brcond_tl 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4008 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-02 18:20:59 +00:00
blueswir1
bffd92fed9 Fix compiler warning 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4003 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-02-29 19:36:08 +00:00
blueswir1
2f0a500803 Fix register references (Igor Kovalenko) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4002 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-02-29 19:34:39 +00:00
blueswir1
8289b27975 Preliminary Sparc TCG target 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3995 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-02-27 17:53:27 +00:00
blueswir1
56b8f567d8 Fix mixed defines 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3992 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-02-25 18:29:19 +00:00
blueswir1
f8422f52fd More helper types, rearrange generic definitions 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3988 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-02-24 07:45:43 +00:00
blueswir1
7089442cb6 Fix andi, optimize addi and subi zero cases 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3985 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-02-20 18:01:23 +00:00
blueswir1
a0d69e0097 Fix typo 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3983 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-02-17 08:45:04 +00:00
pbrook
623e265c6b Simplify TCG relocation bugfix. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3974 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-02-10 14:09:09 +00:00
pbrook
2ba1eeb62c Fix TCG relocation bug (exposed by fault after brcond op). Add FIXME for 
annother potential bug.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3968 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-02-10 02:41:15 +00:00
bellard
3fe43da737 win32: suppress alloca() warning 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3966 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-02-04 22:03:16 +00:00
bellard
5ff9d6a469 fixed sign extensions - added explicit side effect op flag - added discard instruction 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3963 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-02-04 00:37:54 +00:00
bellard
bb210e78b3 compare fix 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3962 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-02-03 21:06:23 +00:00
pbrook
ac56dd4812 Add TCG variable opaque type. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3961 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-02-03 19:56:33 +00:00
bellard
9804c8e203 typos 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3945 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-02-01 13:01:47 +00:00
bellard
c896fe29d6 TCG code generator 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3943 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-02-01 10:05:41 +00:00