Implement TCG rotation ops for x86-64
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6795 c046a42c-6fe2-441c-8c8c-71466251a162
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aurel32
parent
a1f6684d65
commit
d42f183c04
28
tcg/tcg-op.h
28
tcg/tcg-op.h
@ -1573,6 +1573,9 @@ static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
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static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
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{
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#ifdef TCG_TARGET_HAS_rot_i32
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tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2);
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#else
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TCGv_i32 t0, t1;
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t0 = tcg_temp_new_i32();
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@ -1583,10 +1586,14 @@ static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
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tcg_gen_or_i32(ret, t0, t1);
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tcg_temp_free_i32(t0);
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tcg_temp_free_i32(t1);
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#endif
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}
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static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
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{
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#ifdef TCG_TARGET_HAS_rot_i64
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tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2);
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#else
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TCGv_i64 t0, t1;
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t0 = tcg_temp_new_i64();
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@ -1597,6 +1604,7 @@ static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
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tcg_gen_or_i64(ret, t0, t1);
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(t1);
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#endif
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}
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static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
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@ -1605,6 +1613,11 @@ static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
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if (arg2 == 0) {
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tcg_gen_mov_i32(ret, arg1);
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} else {
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#ifdef TCG_TARGET_HAS_rot_i32
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TCGv_i32 t0 = tcg_const_i32(arg2);
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tcg_gen_rotl_i32(ret, arg1, t0);
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tcg_temp_free_i32(t0);
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#else
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TCGv_i32 t0, t1;
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t0 = tcg_temp_new_i32();
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t1 = tcg_temp_new_i32();
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@ -1613,6 +1626,7 @@ static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
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tcg_gen_or_i32(ret, t0, t1);
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tcg_temp_free_i32(t0);
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tcg_temp_free_i32(t1);
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#endif
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}
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}
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@ -1622,6 +1636,11 @@ static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
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if (arg2 == 0) {
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tcg_gen_mov_i64(ret, arg1);
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} else {
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#ifdef TCG_TARGET_HAS_rot_i64
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TCGv_i64 t0 = tcg_const_i64(arg2);
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tcg_gen_rotl_i64(ret, arg1, t0);
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tcg_temp_free_i64(t0);
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#else
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TCGv_i64 t0, t1;
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t0 = tcg_temp_new_i64();
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t1 = tcg_temp_new_i64();
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@ -1630,11 +1649,15 @@ static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
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tcg_gen_or_i64(ret, t0, t1);
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(t1);
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#endif
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}
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}
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static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
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{
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#ifdef TCG_TARGET_HAS_rot_i32
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tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2);
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#else
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TCGv_i32 t0, t1;
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t0 = tcg_temp_new_i32();
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@ -1645,10 +1668,14 @@ static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
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tcg_gen_or_i32(ret, t0, t1);
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tcg_temp_free_i32(t0);
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tcg_temp_free_i32(t1);
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#endif
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}
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static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
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{
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#ifdef TCG_TARGET_HAS_rot_i64
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tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2);
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#else
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TCGv_i64 t0, t1;
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t0 = tcg_temp_new_i64();
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@ -1659,6 +1686,7 @@ static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
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tcg_gen_or_i64(ret, t0, t1);
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(t1);
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#endif
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}
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static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
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@ -67,10 +67,12 @@ DEF2(divu2_i32, 2, 3, 0, 0)
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DEF2(and_i32, 1, 2, 0, 0)
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DEF2(or_i32, 1, 2, 0, 0)
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DEF2(xor_i32, 1, 2, 0, 0)
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/* shifts */
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/* shifts/rotates */
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DEF2(shl_i32, 1, 2, 0, 0)
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DEF2(shr_i32, 1, 2, 0, 0)
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DEF2(sar_i32, 1, 2, 0, 0)
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DEF2(rotl_i32, 1, 2, 0, 0)
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DEF2(rotr_i32, 1, 2, 0, 0)
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DEF2(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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#if TCG_TARGET_REG_BITS == 32
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@ -120,10 +122,12 @@ DEF2(divu2_i64, 2, 3, 0, 0)
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DEF2(and_i64, 1, 2, 0, 0)
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DEF2(or_i64, 1, 2, 0, 0)
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DEF2(xor_i64, 1, 2, 0, 0)
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/* shifts */
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/* shifts/rotates */
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DEF2(shl_i64, 1, 2, 0, 0)
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DEF2(shr_i64, 1, 2, 0, 0)
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DEF2(sar_i64, 1, 2, 0, 0)
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DEF2(rotl_i64, 1, 2, 0, 0)
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DEF2(rotr_i64, 1, 2, 0, 0)
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DEF2(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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#ifdef TCG_TARGET_HAS_ext8s_i64
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@ -194,6 +194,8 @@ static inline int tcg_target_const_match(tcg_target_long val,
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#define ARITH_XOR 6
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#define ARITH_CMP 7
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#define SHIFT_ROL 0
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#define SHIFT_ROR 1
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#define SHIFT_SHL 4
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#define SHIFT_SHR 5
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#define SHIFT_SAR 7
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@ -1049,7 +1051,13 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
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case INDEX_op_sar_i32:
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c = SHIFT_SAR;
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goto gen_shift32;
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case INDEX_op_rotl_i32:
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c = SHIFT_ROL;
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goto gen_shift32;
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case INDEX_op_rotr_i32:
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c = SHIFT_ROR;
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goto gen_shift32;
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case INDEX_op_shl_i64:
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c = SHIFT_SHL;
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gen_shift64:
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@ -1070,7 +1078,13 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
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case INDEX_op_sar_i64:
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c = SHIFT_SAR;
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goto gen_shift64;
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case INDEX_op_rotl_i64:
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c = SHIFT_ROL;
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goto gen_shift64;
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case INDEX_op_rotr_i64:
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c = SHIFT_ROR;
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goto gen_shift64;
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case INDEX_op_brcond_i32:
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tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
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args[3], 0);
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@ -1230,6 +1244,8 @@ static const TCGTargetOpDef x86_64_op_defs[] = {
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{ INDEX_op_shl_i32, { "r", "0", "ci" } },
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{ INDEX_op_shr_i32, { "r", "0", "ci" } },
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{ INDEX_op_sar_i32, { "r", "0", "ci" } },
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{ INDEX_op_rotl_i32, { "r", "0", "ci" } },
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{ INDEX_op_rotr_i32, { "r", "0", "ci" } },
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{ INDEX_op_brcond_i32, { "r", "ri" } },
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@ -1259,6 +1275,8 @@ static const TCGTargetOpDef x86_64_op_defs[] = {
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{ INDEX_op_shl_i64, { "r", "0", "ci" } },
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{ INDEX_op_shr_i64, { "r", "0", "ci" } },
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{ INDEX_op_sar_i64, { "r", "0", "ci" } },
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{ INDEX_op_rotl_i64, { "r", "0", "ci" } },
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{ INDEX_op_rotr_i64, { "r", "0", "ci" } },
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{ INDEX_op_brcond_i64, { "r", "re" } },
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@ -65,6 +65,8 @@ enum {
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#define TCG_TARGET_HAS_ext8s_i64
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#define TCG_TARGET_HAS_ext16s_i64
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#define TCG_TARGET_HAS_ext32s_i64
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#define TCG_TARGET_HAS_rot_i32
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#define TCG_TARGET_HAS_rot_i64
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/* Note: must be synced with dyngen-exec.h */
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#define TCG_AREG0 TCG_REG_R14
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