Commit Graph

816 Commits

Author SHA1 Message Date
Edgar E. Iglesias
95070372f7 powerpc: Add a ppc-440x5 Xilinx model
Add a powerpc 440x5 with the model ID on the Xilinx virtex5.
Connect the 440x5 to the 40x interrupt logic.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2010-09-30 18:53:26 +02:00
Edgar E. Iglesias
a586e548fb powerpc: Improve emulation of the BookE MMU
Improve the emulation of the BookE MMU to be able to boot linux
on virtex5 boards.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2010-09-24 22:01:20 +02:00
Blue Swirl
d62d28630d PPC: Suppress gcc warnings with -Wtype-limits
The hack added by c5b76b3810 was not
enough to avoid warnings with gcc flag -Wtype-limits. Add a new macro
to fix both problems.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-09-18 05:53:15 +00:00
Alexander Graf
41557447d3 PPC: Redesign interrupt trigger path
According to the Book3S spec, the interrupt context starts with an MSR
value that is rather simple. If we leave out the HV case, it's almost
always 0.

To reflect this, let's redesign the way that MSR value gets calculated.
Using this, we also squash the bug where MSR_POW can slip through into
the interrupt handler MSR.

Reported-by: Thomas Monjalon <thomas.monjalon@openwide.fr>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2010-09-15 16:18:33 +02:00
Alexander Graf
f844c817d7 PPC: Enable hint bits for lwarx/ldarx
The lwarx and ldarx instructions have a bit to give some hint to the
CPU which is safe to ignore. We currently refuse to accept any instruction
with that bit set, as it used to be declared MBZ.

Let's remove the reserved bit and make the instruction work as expected.
This fixes Linux boot for ppc64.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Andreas Färber <andreas.faerber@web.de>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2010-09-15 16:18:27 +02:00
Edgar E. Iglesias
24e0e38b83 powerpc: Avoid TLB related log spamming
Invalid TLB entries are normal and should not spam the log.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2010-09-11 14:29:07 +02:00
Alexander Graf
fc87e18530 KVM: PPC: Add level based interrupt logic
KVM on PowerPC used to have completely broken interrupt logic. Usually,
interrupts work by having a PIC that pulls a line up/down, so the CPU knows
that an interrupt is active. This line stays active until some action is
done to the PIC to release the line.

On KVM for PPC, we just checked if there was an interrupt pending and pulled
a line in the kernel module. We never released it though, hoping that kernel
space would just declare an interrupt as released when injected - which is
wrong.

To fix this, we need to completely redesign the interrupt injection logic.
Whenever an interrupt line gets triggered, we need to notify kernel space
that the line is up. Whenever it gets released, we do the same. This way
we can assure that the interrupt state is always known to kernel space.

This fixes random stalls in KVM guests on PowerPC that were waiting for
an interrupt while everyone else thought they received it already.

Signed-off-by: Alexander Graf <agraf@suse.de>
2010-09-05 11:50:48 +02:00
Alexander Graf
45024f094c PPC: Add PV hypercall transport through fw_cfg
On KVM for PPC we need to tell the guest which instructions to use when
doing a hypercall. The clean way to do this is to go through an ioctl
from userspace and passing it on to the guest using the device tree.

So let's do the qemu part here: read out the hypercall and pass it on
to the guest's fw_cfg so openBIOS can read it out and expose it again.

Signed-off-by: Alexander Graf <agraf@suse.de>
2010-08-26 18:13:38 +02:00
Aurelien Jarno
488243b0e9 target-ppc: fix power mode checking on 7400/7410
Only the PowerPC 7440/7450 family don't support DOZE mode. PowerPC
7400 and 7410 support it.
2010-07-19 00:33:29 +02:00
Aurelien Jarno
0bffbc6c7d target-ppc: add vexptefp instruction
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-13 18:18:32 +02:00
Paolo Bonzini
a88790a14f remove exec-all.h inclusion from cpu.h
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-03 09:48:24 +03:00
Paolo Bonzini
10eb0cc03c move cpu_pc_from_tb to target-*/exec.h
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-03 09:48:12 +03:00
Richard Henderson
2bece2c883 tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts.
Some hosts (amd64, ia64) have an ABI that ignores the high bits
of the 64-bit register when passing 32-bit arguments.  Others
require the value to be properly sign-extended for the type.
I.e. "int32_t" must be sign-extended and "uint32_t" must be
zero-extended to 64-bits.

To effect this, extend the "sizemask" parameter to tcg_gen_callN
to include the signedness of the type of each parameter.  If the
tcg target requires it, extend each 32-bit argument into a 64-bit
temp and pass that to the function call.

This ABI feature is required by sparc64, ppc64 and s390x.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-16 11:29:11 +02:00
Thomas Monjalon
0f89cc7b6c target-ppc: remove useless line
This line was a bit clear.
The next lines set or reset this bit (LE) depending of another bit (ILE).
So the first line is useless.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-31 19:18:25 +02:00
Thomas Monjalon
c3d420ead1 target-ppc: fix RFI by clearing some bits of MSR
Since commit 2ada0ed, "Return From Interrupt" is broken for PPC processors
because some interrupt specifics bits of SRR1 are copied to MSR.

SRR1 is a save of MSR during interrupt.
During RFI, MSR must be restored from SRR1.
But some bits of SRR1 are interrupt-specific and are not used for MSR saving.

This is the specification (ISA 2.06) at chapter 6.4.3 (Interrupt Processing):
"2. Bits 33:36 and 42:47 of SRR1 or HSRR1 are loaded with information specific
    to the interrupt type.
 3. Bits 0:32, 37:41, and 48:63 of SRR1 or HSRR1 are loaded with a copy of the
    corresponding bits of the MSR."

Below is a representation of MSR bits which are not saved:
0:15 16:31 32  33:36    37:41      42:47     48:63
——— | ——— | — X X X X — — — — — X X X X X X | ————
0000 0000 |    7   |   8   |   3   |   F    | 0000

History:
In the initial Qemu implementation (e1833e1), the mask 0x783F0000 was used for
saving MSR in SRR1. But all the bits 32:47 were cleared during RFI restoring.
This was wrong. The commit 2ada0ed explains that this breaks Altivec.
Indeed, bit 38 (for Altivec support) must be saved and restored.
The change of 2ada0ed was to restore all the bits of SRR1 to MSR.
But it's also wrong.

Explanation:
As an example, let's see what's happening after a TLB miss.
According to the e300 manual (E300CORERM table 5-6), the TLB miss interrupts
set the bits 44-47 for KEY, I/D, WAY and S/L. These bits are specifics to the
interrupt and must not be copied into MSR at the end of the interrupt.
With the current implementation, a TLB miss overwrite bits POW, TGPR and ILE.

Fix:
It shouldn't be needed to filter-out bits on MSR saving when interrupt occurs.
Specific bits overwrite MSR ones in SRR1.
But at the end of interrupt (RFI), specifics bits must be cleared before
restoring MSR from SRR1. The mask 0x783F0000 apply here.

Discussion:
The bits of the mask 0x783F0000 are cleared after an interrupt.
I cannot find a specification which talks about this
but I assume it is the truth since Linux can run this way.
Maybe it's not perfect but it's better (works for e300).

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-31 19:17:44 +02:00
Blue Swirl
0bfcd599e3 Fix %lld or %llx printf format use
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-22 08:02:12 +00:00
Alexander Graf
c821c2bd4f PPC/KVM: make iothread work
When running with --enable-io-thread the timer we have doesn't help,
because it doesn't wake up the CPU thread. So instead we need to
actually kick it.

While at it I refined the logic a bit to not dumbly trigger a timer
every 500ms, but rather do it more often after an interrupt got injected.
If there's no level based interrupt to be expected, we don't need the
timer anyways.

This makes qemu-system-ppc with --enable-io-thread work when using KVM.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-18 20:21:00 +02:00
Gleb Natapov
4513d9232b Do not stop VM if emulation failed in userspace.
Continue vcpu execution in case emulation failure happened while vcpu
was in userspace. In this case #UD will be injected into the guest
allowing guest OS to kill offending process and continue.

Signed-off-by: Gleb Natapov <gleb@redhat.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-05-11 14:03:44 -03:00
Marcelo Tosatti
0af691d779 kvm: enable smp > 1
Process INIT/SIPI requests and enable -smp > 1.

Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
2010-05-11 14:02:22 -03:00
Richard Henderson
8d0d2eb6b2 target-ppc: Remove duplicate cpu log.
Logging for -d cpu is done in generic code.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-05 12:20:05 +02:00
Blue Swirl
05f92404cd ppc: remove dead assignments, spotted by clang analyzer
Value stored is never read.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-04-25 20:32:49 +00:00
Blue Swirl
7b13448f05 PPC: avoid function pointer type mismatch, spotted by clang
Fixes clang errors:
  CC    ppc-softmmu/translate.o
/src/qemu/target-ppc/translate.c:3748:13: error: comparison of distinct pointer types ('void (*)(void *, int, int)' and 'void *')
        if (likely(read_cb != SPR_NOACCESS)) {
/src/qemu/target-ppc/translate.c:3748:28: note: instantiated from:
        if (likely(read_cb != SPR_NOACCESS)) {
/src/qemu/target-ppc/translate.c:3903:13: error: comparison of distinct pointer types ('void (*)(void *, int, int)' and 'void *')
        if (likely(write_cb != SPR_NOACCESS)) {
/src/qemu/target-ppc/translate.c:3903:29: note: instantiated from:
        if (likely(write_cb != SPR_NOACCESS)) {

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-04-18 14:26:51 +00:00
Dmitry Ilyevsky
de6a1deccf target-ppc: generic PowerPC TBL
Time base SPRs TBL/TBU should be accessible in user/priv modes for reading 
as specified in POWER ISA documentation. Therefore SPRs permissions were 
changed in gen_tbl function.

Signed-off-by: Dmitry Ilyevsky <ilyevsky@gmail.com>
Acked-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26 23:37:23 +01:00
Paul Brook
d4c430a80f Large page TLB flush
QEMU uses a fixed page size for the CPU TLB.  If the guest uses large
pages then we effectively split these into multiple smaller pages, and
populate the corresponding TLB entries on demand.

When the guest invalidates the TLB by virtual address we must invalidate
all entries covered by the large page.  However the address used to
invalidate the entry may not be present in the QEMU TLB, so we do not
know which regions to clear.

Implementing a full vaiable size TLB is hard and slow, so just keep a
simple address/mask pair to record which addresses may have been mapped by
large pages.  If the guest invalidates this region then flush the
whole TLB.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-17 02:44:41 +00:00
Paul Brook
3c7b48b74c Target specific usermode cleanup
Disable various target specific code that is only relevant to system emulation.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-12 18:44:24 +00:00
Paul Brook
4fcc562bff Remove cpu_get_phys_page_debug from userspace emulation
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-12 18:34:25 +00:00
Richard Henderson
5270589032 Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.
Removes a set of ifdefs from exec.c.

Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other
than Alpha.  This will be used for page_find_alloc, which is
supposed to be using virtual addresses in the first place.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2010-03-12 16:28:24 +00:00
Aurelien Jarno
0aef4261ac target-ppc: fix evsrwu and evsrws (second try)
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-11 21:29:42 +01:00
Aurelien Jarno
26b14dc4ab target-ppc: fix evsrwu and evsrws
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-11 21:22:35 +01:00
Aurelien Jarno
e29ef9fabe target-ppc: fix evslw instruction
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-11 21:14:47 +01:00
Jan Kiszka
ea375f9ab8 KVM: Rework VCPU state writeback API
This grand cleanup drops all reset and vmsave/load related
synchronization points in favor of four(!) generic hooks:

- cpu_synchronize_all_states in qemu_savevm_state_complete
  (initial sync from kernel before vmsave)
- cpu_synchronize_all_post_init in qemu_loadvm_state
  (writeback after vmload)
- cpu_synchronize_all_post_init in main after machine init
- cpu_synchronize_all_post_reset in qemu_system_reset
  (writeback after system reset)

These writeback points + the existing one of VCPU exec after
cpu_synchronize_state map on three levels of writeback:

- KVM_PUT_RUNTIME_STATE (during runtime, other VCPUs continue to run)
- KVM_PUT_RESET_STATE   (on synchronous system reset, all VCPUs stopped)
- KVM_PUT_FULL_STATE    (on init or vmload, all VCPUs stopped as well)

This level is passed to the arch-specific VCPU state writing function
that will decide which concrete substates need to be written. That way,
no writer of load, save or reset functions that interact with in-kernel
KVM states will ever have to worry about synchronization again. That
also means that a lot of reasons for races, segfaults and deadlocks are
eliminated.

cpu_synchronize_state remains untouched, just as Anthony suggested. We
continue to need it before reading or writing of VCPU states that are
also tracked by in-kernel KVM subsystems.

Consequently, this patch removes many cpu_synchronize_state calls that
are now redundant, just like remaining explicit register syncs.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-03-04 00:29:28 -03:00
Aurelien Jarno
6c71232122 target-ppc: don't print invalid opcode messages on the console
Invalid opcode messages can be perfectly normal, for example if this
code is never executed. Don't print an error message on the console,
but keep the message in the log for debugging purposes.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-28 16:36:44 +01:00
Aurelien Jarno
db9a231d1f Revert "target-ppc: stop translation after a trap instruction"
This reverts commit 6454e7be1b.
2010-02-28 16:36:44 +01:00
Aurelien Jarno
6454e7be1b target-ppc: stop translation after a trap instruction
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-28 14:11:06 +01:00
Nathan Froyd
ae01847f9c target-ppc: fix SPE evsplat* instructions
The shifts in the gen_evsplat* functions were expecting rA to be masked,
not extracted, and so used the wrong shift amounts to sign-extend or pad
with zeroes.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-27 16:10:50 +01:00
Nathan Froyd
e6bba2ef49 target-ppc: fix SPE evcmp* instructions
The CRF_{CH,CL,CH_OR_CL,CH_AND_CL} constants were all off by one bit
position.  Because of this, the SPE evcmp* family of instructions would
store values in the result condition register that were also off by one
bit position.

Fixed by using the CRF_{LT,GT,EQ,SO} constants for the shift amounts.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-27 16:10:49 +01:00
Alexander Graf
c6a94ba5f9 PPC: Add timer when running KVM
For some odd reason we sometimes hang inside KVM forever. I'd guess it's
a race condition where we actually have a level triggered interrupt, but
the infrastructure can't expose that yet, so the guest ACKs it, goes to
sleep and never gets notified that there's still an interrupt pending.

As a quick workaround, let's just wake up every 500 ms. That way we can
assure that we're always reinjecting interrupts in time.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2010-02-14 16:10:54 +02:00
Alexander Graf
b2eca4453f PPC: Fix large pages
We were masking 1TB SLB entries on the feature bit of 16 MB pages. Obviously
that breaks, so let's just ignore 1TB SLB entries for now and instead do
16MB pages correctly.

This fixes PPC64 Linux boot with -m above 256.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2010-02-14 16:10:54 +02:00
Alexander Graf
dc333cd609 PPC: tell the guest about the time base frequency
Our guest systems need to know by how much the timebase increases every second,
so there usually is a "timebase-frequency" property in the cpu leaf of the
device tree.

This property is missing in OpenBIOS.

With qemu, Linux's fallback timebase speed and qemu's internal timebase speed
match up. With KVM, that is no longer true. The guest is running at the same
timebase speed as the host.

This leads to massive timing problems. On my test machine, a "sleep 2" takes
about 14 seconds with KVM enabled.

This patch exports the timebase frequency to OpenBIOS, so it can then put them
into the device tree.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2010-02-14 16:10:54 +02:00
Aurelien Jarno
95ff895f79 target-ppc: change DCR helpers to target_long arguments
The recent transition to always have the DCR helper functions take 32 bit
values broke the PPC64 target, as target_long became 64 bits there.

This patch changes DCR helpers to target_long arguments, and cast the values
to 32 bit when needed.

Fixes PPC64 build with --enable-debug-tcg

Based on a patch from Alexander Graf <agraf@suse.de>
Reported-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-06 17:14:24 +01:00
Paolo Bonzini
49a945a3c0 kill regs_to_env and env_to_regs
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-01-19 16:31:02 -06:00
Edgar E. Iglesias
dcbc9a70af ppc-40x: Correct ESR for zone protection faults.
Raise the zone protection fault in ESR for TLB faults caused by
zone protection bits.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2010-01-14 14:42:30 +01:00
Edgar E. Iglesias
ec5c3e487e ppc-40x: Correct decoding of zone protection bits.
The 40x MMU has 15 zones in the ZPR register.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2010-01-14 14:42:17 +01:00
Edgar E. Iglesias
c5b9729ae9 ppc-40x: Correct check for Endian swapping TLB entries.
Bailout on 40x TLB entries with endianess swapping only if the entry
is valid.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2010-01-14 14:42:08 +01:00
Edgar E. Iglesias
f25359cd87 ppc-40x: Get TLB attributes from TLBLO.
The ZSEL was incorrectly beeing decoded from TLBHI. Decode it from
TLBLO instead.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2010-01-14 14:41:53 +01:00
Alexander Graf
73b01960b4 PPC: Make DCR uint32_t
For what I know DCR is always 32 bits wide, so we should also use uint32_t to
pass it along the stacks.

This fixes a warning when compiling qemu-system-ppc64 with KVM enabled, making
it compile without --disable-werror

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-21 16:03:03 +01:00
Aurelien Jarno
b711de9565 PPC64: Fix alternate timebase
Fix the alternate time base the same way as the default timebase. SPR_ATBL
should return a 64-bit value on 64 bit implementations.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-21 13:52:08 +01:00
Alexander Graf
e3ea652962 PPC64: Fix timebase
On PPC we have a 64-bit time base. Usually (PPC32) this is accessed using
two separate 32 bit SPR accesses to SPR_TBU and SPR_TBL.

On PPC64 the SPR_TBL register acts as 64 bit though, so we get the full
64 bits as return value. If we only take the lower ones, fine. But Linux
wants to see all 64 bits or it breaks.

This patch makes PPC64 Linux work even after TB crossed the 32-bit boundary,
which usually happened a few seconds after bootup.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-21 13:42:37 +01:00
Alexander Graf
82c09f2f0d target-ppc: fix ppc32 kvm build
My segment sync patch broke compilation on PPC32, because it was trying to
sync the SLB even though ppc32 CPUs don't have an SLB.

So let's only sync it when we're on a PP64 one!

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-19 09:30:20 +01:00
Alexander Graf
ba5e50908c target-ppc: Get MMU state on register sync
While x86 only needs to sync cr0-4 to know all about its MMU state and enable
qemu to resolve virtual to physical addresses, we need to sync all of the
segment registers on PPC to know which mapping we're in.

So let's grab the segment register contents to be able to use the "x" monitor
command and also enable the gdbstub to resolve virtual addresses.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-03 20:10:54 +01:00
Jan Kiszka
caa5af0ff3 kvm: Add arch reset handler
Will be required by succeeding changes.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-11-17 08:49:37 -06:00
Hollis Blanchard
812151f290 kvm ppc: Remove unused label
Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-11-12 11:23:55 -06:00
Blue Swirl
b55a37c981 user: move CPU reset call to main.c for x86/PPC/Sparc
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-11-07 10:37:06 +00:00
Blue Swirl
d84bda46de PPC: rename cpu_ppc_reset to cpu_reset for consistency
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-11-07 10:36:04 +00:00
Blue Swirl
e43941318d PPC: remove unneeded calls to device reset
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-11-07 09:32:21 +00:00
Aurelien Jarno
cb2dbfc351 target-ppc: move often used CPU fields at the top of the structure
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-23 00:14:05 +02:00
Thomas Monjalon
74d77caeed target-ppc: simpler definitions for microcontrollers based on e300
No need to alias e300 core for each CPU package.
Differences between microcontrollers have to be implemented in a higher layer
than translate_init.c

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-18 16:15:47 +02:00
Thomas Monjalon
492d7bf5e9 target-ppc: add declarations of microcontrollers based on e300
Add CPU declarations of MPC8343, MPC8343E, MPC8347 and MPC8347E.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-18 16:15:39 +02:00
Thomas Monjalon
8daf178168 target-ppc: better support of e300 CPU core
Declare HID2 register.

Use high BATs for e300 (8 instead of 4).

Fix index of high BATs registers.
Before the fix, IBAT4-7 were overwriting IBAT0-3.

Signed-off-by: François Armand <francois.armand@os4i.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-18 16:15:34 +02:00
Anthony Liguori
c227f0995e Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem.  Something
like this _must_ be presented on the list first so people can provide input
and cope with it.

This reverts commit 99a0949b72.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01 16:12:16 -05:00
malc
99a0949b72 Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the time
being.

Signed-off-by: malc <av1474@comtv.ru>
2009-10-01 22:45:02 +04:00
Aurelien Jarno
731c54f869 target-ppc: log instructions start in TCG code
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-28 13:40:12 +02:00
Juan Quintela
86178a576b static and inline should came before the type of the functions
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-25 19:51:45 +00:00
Aurelien Jarno
7fd6bf7dae target-ppc: optimize slw/srw/sld/srd
Remove a temp local variable and a jump by computing a mask with shifts.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-18 16:57:33 +02:00
Blue Swirl
72cf2d4f0e Fix sys-queue.h conflict for good
Problem: Our file sys-queue.h is a copy of the BSD file, but there are
some additions and it's not entirely compatible. Because of that, there have
been conflicts with system headers on BSD systems. Some hacks have been
introduced in the commits 15cc923584,
f40d753718,
96555a96d7 and
3990d09adf but the fixes were fragile.

Solution: Avoid the conflict entirely by renaming the functions and the
file. Revert the previous hacks.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-12 07:36:22 +00:00
Juan Quintela
6ee093c907 Unexport ticks_per_sec variable. Create get_ticks_per_sec() function
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-09-11 10:19:52 -05:00
Avi Kivity
4c0960c0c4 kvm: Simplify cpu_synchronize_state()
cpu_synchronize_state() is a little unreadable since the 'modified'
argument isn't self-explanatory.  Simplify it by making it always
synchronize the kernel state into qemu, and automatically flush the
registers back to the kernel if they've been synchronized on this
exit.

Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-08-27 20:35:30 -05:00
Nathan Froyd
0b5c1ce846 cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal
handle_cpu_signal is very nearly copy-paste code for each target, with a
few minor variations.  This patch sets up appropriate defaults for a
generic handle_cpu_signal and provides overrides for particular targets
that did things differently.  Fixing things like the persistent (XXX:
use sigsetjmp) should now become somewhat easier.

Previous comments on this patch suggest that the "activate soft MMU for
this block" comments refer to defunct functionality.  I have removed
such blocks for the appropriate targets in this patch.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-08-24 08:21:42 -05:00
Blue Swirl
b11ebf64b6 Replace REGX with PRIx64
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-16 11:54:37 +00:00
Blue Swirl
90e189ece1 Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plx
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-16 11:13:18 +00:00
Blue Swirl
636aa20056 Replace always_inline with inline
We define inline as always_inline.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-16 09:06:54 +00:00
Nathan Froyd
4425265beb target-ppc: add exceptions for conditional stores
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: malc <av1474@comtv.ru>
2009-08-03 20:33:41 +04:00
Nathan Froyd
18b21a2f83 target-ppc: retain l{w,d}arx loaded value
We do this so we can check on the corresponding stc{w,d}x. whether the
value has changed.  It's a poor man's form of implementing atomic
operations and is valid only for NPTL usermode Linux emulation.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: malc <av1474@comtv.ru>
2009-08-03 20:33:41 +04:00
Nathan Froyd
174c80d516 target-ppc: add cpu_set_tls
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: malc <av1474@comtv.ru>
2009-08-03 20:33:41 +04:00
Nathan Froyd
d11f69b201 target-ppc: fix cpu_clone_regs
We only need to make sure that the clone syscall looks like it
succeeded, not clobber 60% of the register set.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: malc <av1474@comtv.ru>
2009-08-03 20:33:40 +04:00
Juan Quintela
e2542fe2bc rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-27 14:09:21 -05:00
Juan Quintela
3f0855b14b Rename HAVE_FDT to CONFIG_FDT and define it also in Makefile
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-27 14:09:19 -05:00
Alexander Graf
16415335be Use correct input constant
440 and desktop codes use different input constants for interrupt indication.

Let's use the respective ones for KVM.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-22 10:58:46 -05:00
Alexander Graf
861bbc8052 Set PVR in sregs
We need to tell the kernel about some initial CPU state we don't have yet,
so let's use the "sregs" IOCTL for that and simply put the Processor Version
Register in there.

Now the kernel knows which guest CPU to virtualize.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-22 10:58:45 -05:00
Blue Swirl
0bf9e31af1 Fix most warnings (errors with -Werror) when debugging is enabled
I used the following command to enable debugging:
perl -p -i -e 's/^\/\/#define DEBUG/#define DEBUG/g' * */* */*/*

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-20 17:19:25 +00:00
Blue Swirl
8167ee8839 Update to a hopefully more future proof FSF address
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-16 20:47:01 +00:00
Baojun Wang
f407823616 target-ppc: enable PPC_MFTB for 44x
According to PPC440 user manual, PPC 440 supports ``mftb'' even it's a
preserved instruction:

PPC440_UM2013.pdf, p.445, table A-3

when I compile a kernel (2.6.30, bamboo_defconfig/440EP &
canyonlands/460EX), I can see ``mftb'' by using ppc-xxx-objdump
vmlinux

I have also checked the ppc 440x[456], 460S, 464, they also should support mftb.

The following patch enable mftb for all ppc 440 variants, including:
440EP, 440GP, 440x4, 440x5 and 460

Signed-off-by: Baojun Wang <wangbj@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-07-13 01:58:12 +02:00
Baojun Wang
fbe73008f2 ppc tcg: fix wrong bit/mask of wrteei
Signed-off-by: Baojun Wang <wangbj@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-07-13 01:51:17 +02:00
Nathan Froyd
33890b3e0d target-ppc: fix evmergelo and evmergelohi
For 32-bit PPC targets, we translated:

evmergelo rX, rX, rY

as:

rX-lo = rY-lo
rX-hi = rX-lo

which is wrong, because we should be transferring rX-lo first.  This
problem is fixed by swapping the order in which we write the parts of
rX.

Similarly, we translated:

evmergelohi rX, rX, rY

as:

rX-lo = rY-hi
rX-hi = rX-lo

In this case, we can't swap the assignment statements, because that
would just cause problems for:

evmergelohi rX, rY, rX

Instead, we detect the first case and save rX-lo in a temporary
variable:

tmp = rX-lo
rX-lo = rY-hi
rX-hi = tmp

These problems don't occur on PPC64 targets because we don't split the
SPE registers into hi/lo parts for such targets.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-07-12 23:36:21 +02:00
Nathan Froyd
a139aa1751 target-ppc: permit linux-user to read PVR
Access to the PVR SPR is normally forbidden from userspace apps.  The
Linux kernel, however, fixes up reads in the appropriate trap handler.
To permit applications that read PVR to run on QEMU, then, we need to
implement the same handling of PVR reads.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: malc <av1474@comtv.ru>
2009-06-23 21:11:22 +04:00
malc
d2e9fd8f70 Apply TCGV_UNUSED on variables that GCC mistakenly thinks can be used
uninitialized
2009-06-20 05:51:47 +04:00
Blue Swirl
5c55ff99fa Replace ELF section hack with normal table
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-17 15:22:31 +00:00
Blue Swirl
2e6100507a Concentrate rest of table entries to top
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-17 15:22:24 +00:00
Blue Swirl
5462327761 Concentrate most table entries to top
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-17 15:22:19 +00:00
Blue Swirl
e8eaa2c012 Clean up GEN_HANDLER2
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-17 15:22:14 +00:00
Blue Swirl
99e300ef3f Clean up GEN_HANDLER
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-17 15:22:09 +00:00
Blue Swirl
c5b76b3810 Fix mingw32 build warnings
Work around buffer and ioctlsocket argument type signedness problems
Suppress a prototype which is unused on mingw32
Expand a macro to avoid warnings from some GCC versions

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-13 08:44:31 +00:00
Jan Kiszka
b0a46a333a kvm: Add missing bits to support live migration
This patch adds the missing hooks to allow live migration in KVM mode.
It adds proper synchronization before/after saving/restoring the VCPU
states (note: PPC is untested), hooks into
cpu_physical_memory_set_dirty_tracking() to enable dirty memory logging
at KVM level, and synchronizes that drity log into QEMU's view before
running ram_live_save().

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-05-22 10:50:33 -05:00
Anthony Liguori
f80f9ec9a6 Convert machine registration to use module init functions
This cleans up quite a lot of #ifdefs, extern variables, and other ugliness.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-05-21 08:47:55 -05:00
Paul Brook
1ad2134f91 Hardware convenience library
The only target dependency for most hardware is sizeof(target_phys_addr_t).
Build these files into a convenience library, and use that instead of
building for every target.

Remove and poison various target specific macros to avoid bogus target
dependencies creeping back in.

Big/Little endian is not handled because devices should not know or care
about this to start with.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-19 16:17:58 +01:00
Nathan Froyd
c29b735c50 target-ppc: expose cpu capability flags
Do this so other pieces of code can make decisions based on the
capabilities of the CPU we're emulating.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: malc <av1474@comtv.ru>
2009-05-16 01:36:08 +04:00
Paul Brook
5561650587 Include assert.h from qemu-common.h
Include assert.h from qemu-common.h and remove other direct uses.
cpu-all.h still need to include it because of the dyngen-exec.h hacks

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-13 20:54:26 +01:00
malc
1481e16abb Fix typo that leads to out of bounds array access on big endian systems 2009-05-13 15:18:48 +04:00
Tristan Gingold
2d3eb7bfd9 Fix powerpc 604 reset vector
According to 604eUM_book (see 8.3.3 Reset inputs p8-54), the IP bit is set
for hreset and the vector is at offset 0x100 from the exception prefix.

No difference in this area between 604 and 604e.

Signed-off-by: Tristan Gingold <gingold@adacore.com>
2009-04-28 18:07:01 +00:00
Blue Swirl
fc1c67bc2a Fix PPC reset 2009-04-28 18:00:30 +00:00
aliguori
0bf46a40a1 qemu: introduce qemu_init_vcpu (Marcelo Tosatti)
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-24 18:03:41 +00:00
aliguori
6a4955a813 qemu: per-arch cpu_has_work (Marcelo Tosatti)
Blue Swirl: fix Sparc32 breakage

Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7238 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-24 18:03:20 +00:00
aurel32
69a218fc84 target-ppc: mark a few helpers TCG_CALL_CONST and/or TCG_CALL_PURE
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7129 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-16 12:57:58 +00:00
blueswir1
2dc766dafc Fix ppc-softmmu warnings on OpenBSD host
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7099 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-13 16:06:19 +00:00
aurel32
1b530a6dfc Add new command line option -singlestep for tcg single stepping.
This replaces a compile time option for some targets and adds
this feature to targets which did not have a compile time option.

Add monitor command to enable or disable single step mode.

Modify monitor command "info status" to display single step mode.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7004 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-05 20:08:59 +00:00
aurel32
bf1752ef58 target-ppc: Explain why the whole TLB is flushed on SR write
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6947 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-29 13:36:32 +00:00
aurel32
af4b6c54c1 target-ppc: avoid nop to override next instruction
While searching PC, always store the pc of a new instruction.
Instructions that didn't generate tcg code (such as nop) prevented the
next one to be referenced.

Based on patch for target-alpha, r6930.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6931 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-29 01:18:03 +00:00
blueswir1
7f70c93716 Make the ELF loader aware of backwards compatibility
Most 64 bit architectures I'm aware of support running 32 bit code
of the same architecture as well.

So x86_64 can run i386 code easily and ppc64 can run ppc code.

Unfortunately, the current checks are pretty strict. So you can only
load e.g. an x86_64 elf binary on qemu-system-x86_64, but no i386 one.

This can get really annoying. I first encountered this issue with
my multiboot patch, where qemu-system-x86_64 was unable to load an
i386 elf binary because the elf loader rejected it.

The same thing happened again on PPC64 now. The firmware we're loading
is a PPC32 elf binary, as it's shared with PPC32. But the platform is
PPC64.

Right now there is a hack for this in the ppc cpu.h definition, that
simply sets the type to PPC32 in system emulation mode. While that
works fine for the firmware, it's no good if you also want to load a
PPC64 kernel with -kernel.

So in order to solve this mess, I figured the easiest way is to make
the elf loader aware of platforms that are backwards compatible. For
now I was only sure that x86_64 does i386 and ppc64 does ppc32, but
maybe there are other combinations too.

This patch is a prerequisite for having a working -kernel option on
PPC64.

Signed-off-by: Alexander Graf <alex@csgraf.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6855 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-13 21:16:24 +00:00
aurel32
fa3966a3dc target-ppc: use the new bswap* TCG ops
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6835 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-13 09:35:34 +00:00
aurel32
66896cb803 tcg: rename bswap_i32/i64 functions
Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-13 09:34:48 +00:00
aurel32
515e2f7efe target-ppc: fix commit r6789
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6804 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-10 19:37:28 +00:00
aurel32
651721b2a5 targe-ppc: optimize mfcr and mtcrf
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6793 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-09 18:50:24 +00:00
aurel32
69bd582091 target-ppc: free a tcg temp variable
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6790 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-09 06:27:24 +00:00
aurel32
d34defbc21 target-ppc: add support for reading/writing spefscr
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6789 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-09 06:27:14 +00:00
aurel32
70976a7926 Fix off-by-one errors for Altivec and SPE registers
Altivec and SPE both have 34 registers in their register sets, not 35
with a missing register 32.

GDB would ask for register 32 of the Altivec (resp. SPE) registers and
the code would claim it had zero width.  The QEMU GDB stub code would
then return an E14 to GDB, which would complain about not being sure
whether p packets were supported or not.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6769 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 22:00:49 +00:00
blueswir1
9485593725 Disable BAT for 970
The 970 doesn't know BAT, so let's not search BATs there.
This was only in as a hack for OpenHackWare so it would
work on PPC64.

Signed-off-by: Alexander Graf <alex@csgraf.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6759 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 20:58:30 +00:00
aurel32
0497d2f4e4 Fix mfcr on ppc64-softmmu
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6758 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 20:57:47 +00:00
blueswir1
8eee0af947 Keep SLB in-CPU
Real 970 CPUs have the SLB not memory backed, but inside the CPU.
This breaks bridge mode for 970 for now, but at least keeps us from
overwriting physical addresses 0x0 - 0x300, rendering our interrupt
handlers useless.

I put in a stub for bridge mode operation that could be enabled
easily, but for now it's safer to leave that off I guess (970fx doesn't
have bridge mode AFAIK).

Signed-off-by: Alexander Graf <alex@csgraf.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6757 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 20:57:42 +00:00
blueswir1
29c8ca6f2e Fix NX bit
ctx->nx only got ORed, but never reset. So when one page in the
lifetime of the VM was ever NX, all later pages were too.

Signed-off-by: Alexander Graf <alex@csgraf.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6755 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 20:57:01 +00:00
blueswir1
2ada0ed785 Fix RFI(d)
The current implementation masks some MSR bits from SRR1 as it is
given on rfi(d). This looks pretty wrong and breaks Altivec.

Signed-off-by: Alexander Graf <alex@csgraf.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6754 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 20:56:21 +00:00
blueswir1
4911012d26 Implement mtfsf.L encoding
Mtfsf can have the L bit set, so all the register contents get stored
in FPSCR. Linux uses it, so let's implement it.

Signed-off-by: Alexander Graf <alex@csgraf.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6753 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 20:55:31 +00:00
blueswir1
6ce0ca1204 Enable 64bit mode on interrupts
Real 970s enable MSR_SF on all interrupts. The current code didn't do
this until now, so let's activate it!

Signed-off-by: Alexander Graf <alex@csgraf.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6752 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 20:54:59 +00:00
blueswir1
4e98d8cf0a Nop some SPRs on 970fx
Linux tries to access some SPRs on PPC64 boot. Let's just ignore those
for the 970fx for now to make it happy.

Signed-off-by: Alexander Graf <alex@csgraf.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6751 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 20:54:03 +00:00
blueswir1
bf14b1cef1 Implment tlbiel
Linux uses tlbiel to flush TLB entries in PPC64 mode. This special TLB
flush opcode only flushes an entry for the CPU it runs on, not across
all CPUs in the system.

Signed-off-by: Alexander Graf <alex@csgraf.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6749 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 20:52:22 +00:00
blueswir1
5b5aba4f14 Implement large pages
The current SLB/PTE code does not support large pages, which are
required by Linux, as it boots up with the kernel regions up as large.

This patch implements large page support, so we can run Linux.

Signed-off-by: Alexander Graf <alex@csgraf.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6748 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 20:51:18 +00:00
blueswir1
f6b868fc58 Implement slbmte
In order to modify SLB entries on recent PPC64 machines, the slbmte
instruction is used.

This patch implements the slbmte instruction and makes the "bridge"
mode code use the slb set functions, so we can move the SLB into
the CPU struct later.

This is required for Linux to run on PPC64.

Signed-off-by: Alexander Graf <alex@csgraf.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6747 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 20:50:01 +00:00
blueswir1
50773fd23d Sparse fixes: add extern to ELF opcode tables to avoid warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6740 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 15:59:09 +00:00
pbrook
c276471991 The _exit syscall is used for both thread termination in NPTL applications,
and process termination in legacy applications.  Try to guess which we want
based on the presence of multiple threads.

Also implement locking when modifying the CPU list.


Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6735 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 15:24:59 +00:00
aurel32
0cfe11ea5f target-ppc: improve mfcr/mtcrf
- use ctz32 instead of ffs - 1
- small optimisation of mtcrf
- add the name of both opcodes

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6669 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-03 06:12:14 +00:00
malc
8dd640e49d Fix mtcrf/mfcr
Noticed by Alexander Graf

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6667 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-02 22:39:39 +00:00
aurel32
1db09b847e kvm/powerpc: Add MPC8544DS board support
This patch add an emulation of MPC8544DS board.
It can work on All E500 platforms.

Signed-off-by: Liu Yu <yu.liu@freescale.com>
Acked-by: Hollis Blanchard <hollisb@us.ibm.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6663 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-02 16:42:42 +00:00
aurel32
9fdc60bf55 kvm/powerpc: Add irq support for E500 core
Signed-off-by: Liu Yu <yu.liu@freescale.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6662 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-02 16:42:32 +00:00
blueswir1
2adab7d6b5 Implement HIOR
A real 970 CPU starts up with HIOR=0xfff00000 and triggers a reset
exception, basically ending up at IP 0xfff001000.

Later on this HIOR has to be set to 0 by the firmware in order to
enable the OS to handle interrupts on its own.

This patch maps HIOR to exec_prefix, which does the same thing
internally in qemu already.

It replaces the previous patch that changed the 970 initialization
constants, as this is the clean solution to the same problem.

Signed-off-by: Alexander Graf <alex@csgraf.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6656 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-28 18:39:42 +00:00
blueswir1
a457e7ee3d Fix typo in gen_qemu_ld32s
When the CPU is in little endian mode, it should load values from RAM
in byte swapped manner. This check is in all the ld and st functions,
but misspelled in gen_qemu_ld32s.

This patch fixes the misspelling and makes ppc64 Linux happier.

Signed-off-by: Alexander Graf <alex@csgraf.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6654 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-28 08:25:29 +00:00
blueswir1
07c485ce78 Turn MMU off on reset
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6637 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-21 17:29:14 +00:00
blueswir1
5518f3a636 Fix branch debugging
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6629 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-19 20:17:09 +00:00
aurel32
bd5ea51398 target-ppc: Model e500v{1,2} CPUs more accurately
The e500v1 chips only have single-precision floating point; don't say we
support the double-precision floating-point instructions on such chips.
Also add an e500v1 -cpu argument for a generic e500v1.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6576 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 16:50:00 +00:00
aurel32
40569b7edc target-ppc: Model SPE floating-point instructions more accurately
Single-precision and double-precision floating-point instructions should
be separated into their own categories, since some chips only support
single-precision instructions.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6575 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 16:49:50 +00:00
aurel32
071fc3b1cd target-ppc: Add vrsqrtefp instruction
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6574 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 16:49:40 +00:00
aurel32
bdfbac3512 target-ppc: Add vrefp instruction
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6573 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 16:49:29 +00:00
aurel32
875b31db7f target-ppc: Add vct{u,s}xs instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6572 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 16:49:20 +00:00
aurel32
819ca12127 target-ppc: Add vcmp{eq, ge, gt, b}fp{, .} instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6571 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 16:49:10 +00:00
aurel32
35cf7c7e18 target-ppc: Add vmaddfp and vnmsubfp instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6570 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 16:48:59 +00:00
aurel32
56fdd213ef target-ppc: Add v{add,sub}fp instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6569 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 16:48:51 +00:00
aurel32
1536ff641f target-ppc: Add v{max,min}fp instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6568 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 16:48:39 +00:00
blueswir1
3a616592a1 Load 32 bit ELF BIOS images also on PPC64
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6554 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-08 12:50:56 +00:00
aurel32
b580763f86 target-ppc: change instruction name vrlogefp into vlogefp
Thanks to Nathan Froyd for noticing that.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6532 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-05 22:33:36 +00:00
aliguori
0d0266a53b targets: remove error handling from qemu_malloc() callers (Avi Kivity)
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-05 22:06:11 +00:00
aurel32
f586ce09e2 target-ppc: add vrlogefp instruction
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6519 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-05 13:42:57 +00:00
aurel32
06f7332ab9 target-ppc: fix previous commit
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6516 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-04 14:08:08 +00:00
aurel32
c609b12e1f target-ppc: use the new float constants
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6515 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-04 13:52:39 +00:00
aurel32
e140632e87 Add vcf{u,s}x instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6513 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-04 13:52:17 +00:00
aurel32
f6b1964548 Add vrfi{m,n,p,z} instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6512 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-04 13:52:03 +00:00
aurel32
34ba2857a0 Add various NaN-handling macros
These simplify the implementation of the floating-point Altivec
instructions and reduce clutter.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6511 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-04 09:05:53 +00:00
aurel32
6e87b7c7bf Make mtvscr use a helper
Do this so we can set float statuses once per mtvscr, rather than once
per Altivec instruction.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6508 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-03 19:56:09 +00:00
aurel32
cf8358c8f7 Add calls to initialize VSCR on appropriate machines
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6507 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-03 19:55:59 +00:00
aurel32
fbd265b681 Rename spe_status to vec_status
Only one of Altivec and SPE will be available on a given chip.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6506 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-03 19:55:51 +00:00
aurel32
0f6fbcbccd Add f field to ppc_avr_t
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6505 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-03 19:55:43 +00:00
aurel32
fce5ecb780 Fix compilation of PPC64 targets with DEBUG_TCGV enabled
The attached patch fixes compilation of PPC64 targets with DEBUG_TCGV
enabled.

Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6502 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-03 19:55:13 +00:00
aliguori
eca1bdf415 Log reset events (Jan Kiszka)
Original idea&code by Kevin Wolf, split-up in two patches and added more
archs.

This patch introduces a flag to log CPU resets. Useful for tracing
unexpected resets (such as those triggered by x86 triple faults).

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6452 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-26 19:54:31 +00:00
aurel32
ea23bc2022 kvm/powerpc: extern one function for MPC85xx code use
Signed-off-by: Liu Yu <yu.liu@freescale.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6427 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-24 16:35:56 +00:00
aurel32
688890f75e target-ppc: Add SPE register read/write using XML
Don't read/write SPEFSCR until we figure out what to do about exceptions.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6425 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-24 15:08:17 +00:00
aurel32
b4f8d821e5 target-ppc: Add Altivec register read/write using XML
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6424 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-24 15:08:09 +00:00
aurel32
2495152227 target-ppc: Add float register read/write using XML
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6423 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-24 15:08:00 +00:00
aurel32
4e47ea6702 target-ppc: Include gdbstub.h
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6422 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-24 15:07:50 +00:00
aliguori
8fec2b8c45 global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)
These are references to 'loglevel' that aren't on a simple 'if (loglevel &
X) qemu_log()' statement.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6340 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15 22:36:53 +00:00
aliguori
93fcfe39a0 Convert references to logfile/loglevel to use qemu_log*() macros
This is a large patch that changes all occurrences of logfile/loglevel
global variables to use the new qemu_log*() macros.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6338 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15 22:34:14 +00:00
aliguori
d12d51d5ba Clean up debugging code #ifdefs (Eduardo Habkost)
Use macros to avoid #ifdefs on debugging code.

This patch doesn't try to merge logging macros from different files,
but just unify the debugging code #ifdefs onto a macro on each file. A
further cleanup can unify the debugging macros on a common header, later

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6332 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15 21:48:06 +00:00
aliguori
da07cf59b0 powerpc/kvm: enable POWERPC_MMU_BOOKE_FSL when kvm is enabled (Liu Yu)
Signed-off-by: Liu Yu <yu.liu@freescale.com>
Acked-by: Hollis Blanchard <hollisb@us.ibm.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6329 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15 21:24:24 +00:00
aliguori
57be80f948 powerpc/kvm: Fix a uninitialized bug (Liu Yu)
Signed-off-by: Liu Yu <yu.liu@freescale.com>
Acked-by: Hollis Blanchard <hollisb@us.ibm.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6327 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15 21:18:42 +00:00
aurel32
1b6e5f9906 target-ppc: fix wrteei instruction
Patch by Andrew May

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6308 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-14 19:40:54 +00:00
aurel32
ae1c1a3d68 target-ppc: add altivec cache instructions
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6275 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-12 21:33:02 +00:00
aurel32
5ab09f3349 Add v{add, sub}{s, u}{b, h, w}s instructions
Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6254 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-08 23:19:50 +00:00
aurel32
c026766b15 Add vspltis{b,h,w} instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6238 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-08 18:54:57 +00:00
aurel32
d9430add63 Add vs{l,r} instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6237 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-08 18:54:48 +00:00
aurel32
1add6e234a Add vcmpequ{b, h, w} and vcmpgt{s, u}{b, h, w} instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6236 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-08 18:54:38 +00:00
aurel32
0cbcd90636 Add GEN_VXRFORM{,1} macros for subsequent instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6235 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-08 18:54:26 +00:00
aurel32
b392e756c1 target-ppc: fix compilation on BigEndian
This fixes BigEndian compilation for target-ppc.

(Michael Buesch)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6193 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-05 21:40:27 +00:00
aurel32
785f451b62 target-ppc: Add m{f,t}vscr instructions.
Based on a patch by Nathan Froyd <froydnj@codesourcery.com>

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6190 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:51:59 +00:00
aurel32
8142cddda2 Add vsumsws, vsum2sws, and vsum4{sbs, shs,ubs} instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6189 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:13:21 +00:00
aurel32
cbfb6ae9b3 Add {l,st}ve{b,h,w}x instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6188 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:13:10 +00:00
aurel32
bcd2ee23ea Add vmladduhm instruction.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6187 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:13:00 +00:00
aurel32
eae07261c7 Add vmsumsh{m,s} instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6186 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:12:49 +00:00
aurel32
4d9903b6c3 Add vmsumuh{m,s} instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6185 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:12:39 +00:00
aurel32
b161ae2766 Add vmh{,r}addshs instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6184 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:12:29 +00:00
aurel32
1dd9ffb969 Add vpkpx instruction.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6183 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:12:19 +00:00
aurel32
5335a145a1 Add vpks{h, w}{s, u}s, vpku{h, w}us, and vpku{h, w}um instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6182 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:12:09 +00:00
aurel32
00d3b8f59b Add saturating arithmetic conversion functions for subsequent instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6181 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:11:59 +00:00
aurel32
d1258698f5 Add vsel and vperm instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6180 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:11:49 +00:00
aurel32
b04ae9811a Add vmsum{u,m}bm instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6179 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:11:39 +00:00
aurel32
707cec33f0 Add GEN_VAFORM_PAIRED macro for subsequent instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6178 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:11:29 +00:00
aurel32
6cf1c6e547 Add vupk{h,l}s{b,h} instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6177 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:11:20 +00:00
aurel32
79f85c3ae9 Add vupk{h,l}px instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6176 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:11:10 +00:00
aurel32
de5f248499 Add GEN_VXFORM_NOA macro for subsequent instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6175 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:10:59 +00:00
aurel32
e4e6bee787 Add vsplt{b,h,w} instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6174 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:10:49 +00:00
aurel32
27a4edb310 Add GEN_VXFORM_UIMM macro for subsequent instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6173 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:10:40 +00:00
aurel32
21d215831e Add GEN_VXFORM_SIMM macro for subsequent instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6172 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:10:28 +00:00
aurel32
cd633b10fd Add vsldoi instruction.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6171 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:10:09 +00:00
aurel32
5e1d0985f9 Add vrl{b,h,w} instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6170 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:09:52 +00:00
aurel32
bf8d8ded57 Add lvs{l,r} instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6169 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:09:42 +00:00