target-ppc: improve mfcr/mtcrf
- use ctz32 instead of ffs - 1 - small optimisation of mtcrf - add the name of both opcodes Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6669 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -28,6 +28,7 @@
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#include "disas.h"
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#include "tcg-op.h"
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#include "qemu-common.h"
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#include "host-utils.h"
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#include "helper.h"
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#define GEN_HELPER 1
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@ -3836,7 +3837,7 @@ GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
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tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
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}
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/* mfcr */
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/* mfcr mfocrf */
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GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
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{
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uint32_t crm, crn;
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@ -3844,7 +3845,7 @@ GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
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if (likely(ctx->opcode & 0x00100000)) {
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crm = CRM(ctx->opcode);
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if (likely(crm && ((crm & (crm - 1)) == 0))) {
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crn = ffs (crm) - 1;
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crn = ctz32 (crm);
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tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
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tcg_gen_shli_i32(cpu_gpr[rD(ctx->opcode)],
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cpu_gpr[rD(ctx->opcode)], crn * 4);
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@ -3931,7 +3932,7 @@ GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
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gen_op_mfspr(ctx);
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}
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/* mtcrf */
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/* mtcrf mtocrf*/
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GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
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{
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uint32_t crm, crn;
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@ -3940,10 +3941,10 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
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if (likely((ctx->opcode & 0x00100000))) {
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if (crm && ((crm & (crm - 1)) == 0)) {
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TCGv_i32 temp = tcg_temp_new_i32();
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crn = ffs (crm) - 1;
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crn = ctz32 (crm);
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tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
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tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
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tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
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tcg_gen_shri_i32(temp, temp, crn * 4);
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tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
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tcg_temp_free_i32(temp);
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}
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} else {
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@ -24,7 +24,6 @@
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*/
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#include "dis-asm.h"
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#include "host-utils.h"
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#include "gdbstub.h"
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//#define PPC_DUMP_CPU
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