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PPC: remove unneeded calls to device reset

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Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl 2009-11-07 09:32:21 +00:00
parent a01d6ef446
commit e43941318d
13 changed files with 2 additions and 26 deletions
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1
hw/adb.c
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@ -123,7 +123,6 @@ ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
d->devreset = devreset;
d->opaque = opaque;
qemu_register_reset((QEMUResetHandler *)devreset, d);
d->devreset(d);
return d;
}

1
hw/cuda.c
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@ -763,5 +763,4 @@ void cuda_init (int *cuda_mem_index, qemu_irq irq)
*cuda_mem_index = cpu_register_io_memory(cuda_read, cuda_write, s);
register_savevm("cuda", -1, 1, cuda_save, cuda_load, s);
qemu_register_reset(cuda_reset, s);
cuda_reset(s);
}

1
hw/grackle_pci.c
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@ -172,7 +172,6 @@ static int pci_grackle_init_device(SysBusDevice *dev)
register_savevm("grackle", 0, 1, pci_grackle_save, pci_grackle_load,
&s->host_state);
qemu_register_reset(pci_grackle_reset, &s->host_state);
pci_grackle_reset(&s->host_state);
return 0;
}

1
hw/heathrow_pic.c
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@ -231,6 +231,5 @@ qemu_irq *heathrow_pic_init(int *pmem_index,
register_savevm("heathrow_pic", -1, 1, heathrow_pic_save,
heathrow_pic_load, s);
qemu_register_reset(heathrow_pic_reset, s);
heathrow_pic_reset(s);
return qemu_allocate_irqs(heathrow_pic_set_irq, s, 64);
}

1
hw/ide/macio.c
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@ -330,7 +330,6 @@ int pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,
pmac_ide_write, d);
vmstate_register(0, &vmstate_pmac, d);
qemu_register_reset(pmac_ide_reset, d);
pmac_ide_reset(d);
return pmac_ide_memory;
}

1
hw/mac_dbdma.c
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@ -840,7 +840,6 @@ void* DBDMA_init (int *dbdma_mem_index)
*dbdma_mem_index = cpu_register_io_memory(dbdma_read, dbdma_write, s);
register_savevm("dbdma", -1, 1, dbdma_save, dbdma_load, s);
qemu_register_reset(dbdma_reset, s);
dbdma_reset(s);
dbdma_bh = qemu_bh_new(DBDMA_run_bh, s);

1
hw/mac_nvram.c
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@ -143,7 +143,6 @@ MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size,
register_savevm("macio_nvram", -1, 1, macio_nvram_save, macio_nvram_load,
s);
qemu_register_reset(macio_nvram_reset, s);
macio_nvram_reset(s);
return s;
}

2
hw/openpic.c
View File

@ -1254,7 +1254,6 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
opp->irq_raise = openpic_irq_raise;
opp->reset = openpic_reset;
opp->reset(opp);
if (pmem_index)
*pmem_index = opp->mem_index;
@ -1709,7 +1708,6 @@ qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
register_savevm("mpic", 0, 2, openpic_save, openpic_load, mpp);
qemu_register_reset(mpic_reset, mpp);
mpp->reset(mpp);
return qemu_allocate_irqs(openpic_set_irq, mpp, mpp->max_irq);

2
hw/ppc405_boards.c
View File

@ -165,7 +165,6 @@ static void ref405ep_fpga_init (uint32_t base)
fpga_memory = cpu_register_io_memory(ref405ep_fpga_read,
ref405ep_fpga_write, fpga);
cpu_register_physical_memory(base, 0x00000100, fpga_memory);
ref405ep_fpga_reset(fpga);
qemu_register_reset(&ref405ep_fpga_reset, fpga);
}
@ -489,7 +488,6 @@ static void taihu_cpld_init (uint32_t base)
cpld_memory = cpu_register_io_memory(taihu_cpld_read,
taihu_cpld_write, cpld);
cpu_register_physical_memory(base, 0x00000100, cpld_memory);
taihu_cpld_reset(cpld);
qemu_register_reset(&taihu_cpld_reset, cpld);
}

12
hw/ppc405_uc.c
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@ -172,7 +172,6 @@ static void ppc4xx_plb_init(CPUState *env)
ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
ppc4xx_plb_reset(plb);
qemu_register_reset(ppc4xx_plb_reset, plb);
}
@ -250,7 +249,6 @@ static void ppc4xx_pob_init(CPUState *env)
ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
qemu_register_reset(ppc4xx_pob_reset, pob);
ppc4xx_pob_reset(pob);
}
/*****************************************************************************/
@ -387,7 +385,6 @@ static void ppc4xx_opba_init(target_phys_addr_t base)
#endif
io = cpu_register_io_memory(opba_read, opba_write, opba);
cpu_register_physical_memory(base, 0x002, io);
ppc4xx_opba_reset(opba);
qemu_register_reset(ppc4xx_opba_reset, opba);
}
@ -580,7 +577,6 @@ static void ppc405_ebc_init(CPUState *env)
ppc4xx_ebc_t *ebc;
ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
ebc_reset(ebc);
qemu_register_reset(&ebc_reset, ebc);
ppc_dcr_register(env, EBC0_CFGADDR,
ebc, &dcr_read_ebc, &dcr_write_ebc);
@ -672,7 +668,6 @@ static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4])
dma = qemu_mallocz(sizeof(ppc405_dma_t));
memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
ppc405_dma_reset(dma);
qemu_register_reset(&ppc405_dma_reset, dma);
ppc_dcr_register(env, DMA0_CR0,
dma, &dcr_read_dma, &dcr_write_dma);
@ -843,7 +838,6 @@ static void ppc405_gpio_init(target_phys_addr_t base)
#endif
io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio);
cpu_register_physical_memory(base, 0x038, io);
ppc405_gpio_reset(gpio);
qemu_register_reset(&ppc405_gpio_reset, gpio);
}
@ -1001,7 +995,6 @@ static void ppc405_ocm_init(CPUState *env)
ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
ocm->offset = qemu_ram_alloc(4096);
ocm_reset(ocm);
qemu_register_reset(&ocm_reset, ocm);
ppc_dcr_register(env, OCM0_ISARC,
ocm, &dcr_read_ocm, &dcr_write_ocm);
@ -1254,7 +1247,6 @@ static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
#endif
io = cpu_register_io_memory(i2c_read, i2c_write, i2c);
cpu_register_physical_memory(base, 0x011, io);
ppc4xx_i2c_reset(i2c);
qemu_register_reset(ppc4xx_i2c_reset, i2c);
}
@ -1539,7 +1531,6 @@ static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
io = cpu_register_io_memory(gpt_read, gpt_write, gpt);
cpu_register_physical_memory(base, 0x0d4, io);
qemu_register_reset(ppc4xx_gpt_reset, gpt);
ppc4xx_gpt_reset(gpt);
}
/*****************************************************************************/
@ -1763,7 +1754,6 @@ static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4])
mal = qemu_mallocz(sizeof(ppc40x_mal_t));
for (i = 0; i < 4; i++)
mal->irqs[i] = irqs[i];
ppc40x_mal_reset(mal);
qemu_register_reset(&ppc40x_mal_reset, mal);
ppc_dcr_register(env, MAL0_CFG,
mal, &dcr_read_mal, &dcr_write_mal);
@ -2149,7 +2139,6 @@ static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
&dcr_read_crcpc, &dcr_write_crcpc);
ppc405cr_clk_init(cpc);
qemu_register_reset(ppc405cr_cpc_reset, cpc);
ppc405cr_cpc_reset(cpc);
}
CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
@ -2469,7 +2458,6 @@ static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
PPC405EP_CLK_NB * sizeof(clk_setup_t));
cpc->jtagid = 0x20267049;
cpc->sysclk = sysclk;
ppc405ep_cpc_reset(cpc);
qemu_register_reset(&ppc405ep_cpc_reset, cpc);
ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);

2
hw/ppc4xx_devs.c
View File

@ -304,7 +304,6 @@ qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
&dcr_read_uic, &dcr_write_uic);
}
qemu_register_reset(ppcuic_reset, uic);
ppcuic_reset(uic);
return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
}
@ -639,7 +638,6 @@ void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t));
memcpy(sdram->ram_sizes, ram_sizes,
nbanks * sizeof(target_phys_addr_t));
sdram_reset(sdram);
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
sdram, &dcr_read_sdram, &dcr_write_sdram);

1
hw/unin_pci.c
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@ -188,7 +188,6 @@ static int pci_unin_main_init_device(SysBusDevice *dev)
register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, &s->host_state);
qemu_register_reset(pci_unin_reset, &s->host_state);
pci_unin_reset(&s->host_state);
return 0;
}

2
target-ppc/helper.c
View File

@ -2811,7 +2811,9 @@ CPUPPCState *cpu_ppc_init (const char *cpu_model)
ppc_translate_init();
env->cpu_model_str = cpu_model;
cpu_ppc_register_internal(env, def);
#if defined(CONFIG_USER_ONLY)
cpu_ppc_reset(env);
#endif
qemu_init_vcpu(env);