Stanislav Shwartsman
f8185a6bc6
Added Intel VMX emulation to Bochs CPU
2009-01-31 10:43:24 +00:00
Stanislav Shwartsman
0325c120b2
Separate PAUSE instruction from regular NOP
2009-01-27 20:29:05 +00:00
Stanislav Shwartsman
9929e6ed78
- updated FSF address
2009-01-16 18:18:59 +00:00
Stanislav Shwartsman
0ff68a2aa2
Fixed XSAVE decode in x86-64 mode
2009-01-10 16:01:55 +00:00
Stanislav Shwartsman
2066d8b594
Fixed compilation issues
2008-10-06 17:50:06 +00:00
Alexander Krisak
a6cce95418
fixed compillation
2008-09-23 13:25:32 +00:00
Stanislav Shwartsman
db664c4012
more optimizations after fetchdecode
2008-09-16 20:57:16 +00:00
Stanislav Shwartsman
d7fdaaad5b
remove not needed index set
2008-09-16 19:22:13 +00:00
Stanislav Shwartsman
a9c77eb75d
Try to optimize individual instructions after fetchdecode
2008-09-16 19:20:03 +00:00
Stanislav Shwartsman
7566faf948
A bit simplify FPU decoding
2008-09-16 18:28:53 +00:00
Stanislav Shwartsman
d57a211df9
Fixed handling of prefixes for EMMS
...
Small FPU optimization
2008-09-12 20:59:31 +00:00
Stanislav Shwartsman
b03f940807
optimize seg_override decoding
2008-09-08 16:15:59 +00:00
Stanislav Shwartsman
c1306f7d75
small non-significant speedups
2008-09-06 21:10:40 +00:00
Stanislav Shwartsman
b3b2f77675
Reduce size of Bochs static tables by changing from bx_bool (which is 32bit) to Bit8u
2008-09-06 18:21:29 +00:00
Stanislav Shwartsman
0cd11fd385
Updated instrumentation callbacks - removed fetchdecode_completed callback
2008-09-06 17:49:32 +00:00
Stanislav Shwartsman
a0e395188f
Fixed merge error
2008-08-29 20:43:05 +00:00
Stanislav Shwartsman
b96f78dc0a
Some kind of big change in fetchdecode tables invented in order to compress the tables for better host data cache utilization
2008-08-29 19:23:03 +00:00
Stanislav Shwartsman
a5a01c4b42
optimize LEAVE operation
2008-08-27 21:57:40 +00:00
Stanislav Shwartsman
d0803ebd10
branch_16 optimizations
2008-08-23 22:27:58 +00:00
Stanislav Shwartsman
991ae348cb
Clean invalidate_prefetch_q when not needed
2008-08-23 13:55:37 +00:00
Stanislav Shwartsman
70f363a05c
Unroll back 32-bit fetchdecode displ
2008-08-11 21:06:27 +00:00
Stanislav Shwartsman
a8adb36dc2
Implemented MOVBE Intel Atom(R) instruction
2008-08-11 18:53:24 +00:00
Stanislav Shwartsman
b61017e5b6
Split more opcodes using new LOAD technique
2008-08-10 21:16:12 +00:00
Stanislav Shwartsman
1da5943f1a
More use of LOAD_Ex method
2008-08-10 19:34:28 +00:00
Stanislav Shwartsman
0d90ab0478
Completely new way to handle LD+OP cases - allows to significantly reduce number of BX_CPU_C methods
2008-08-09 21:05:07 +00:00
Stanislav Shwartsman
24e0b53720
This more ellegant way to have debug info for BxError and not lose any performace
2008-08-09 19:18:09 +00:00
Stanislav Shwartsman
709d74728d
Call #UD exception directly instead of UndefinedOpcode function - for future use
2008-07-13 15:35:10 +00:00
Stanislav Shwartsman
0127415ba6
Clear some duplicated arithmetic opcodes - difference only in operands order
2008-07-13 09:59:59 +00:00
Stanislav Shwartsman
65275ffc02
Remove repeat speedups from 16-bit address size methods - they not gonna speed up anyway because of segment limit issue
2008-06-25 10:34:21 +00:00
Stanislav Shwartsman
a6fda9a971
Instrumentation code updated, some PANIC messages fixed
2008-06-23 02:56:31 +00:00
Stanislav Shwartsman
678ac970aa
Reorganize ctrl_xfer8.cc code, allows to inline branch32 method
2008-06-22 03:45:55 +00:00
Stanislav Shwartsman
7f82a536b3
Fixed code duplication during prefix decoding
2008-06-11 20:58:29 +00:00
Stanislav Shwartsman
aff775bce4
Small code optimization
2008-06-09 19:35:59 +00:00
Stanislav Shwartsman
ed4be45a8b
Split shift/rotate opcodes in 32-bit mode and 64-bit mode
2008-05-02 22:47:07 +00:00
Stanislav Shwartsman
f5780a5f5c
Hide some BX_MEM_C variables
...
Optimize resolve16 methods - by reducing their amount again - reduce chance for misspredictin
2008-05-01 20:08:37 +00:00
Stanislav Shwartsman
81deffd65d
More fetchdecode fixes
2008-04-30 21:32:33 +00:00
Stanislav Shwartsman
e5b6f90b62
some fetchdecode fixes
2008-04-30 21:07:12 +00:00
Stanislav Shwartsman
64f2489afb
Correctly implement opcode group G11 i.e. instructions C6 and C7 should @UD when modrm nnn field != 0 (1st instr in the group
2008-04-24 21:52:28 +00:00
Stanislav Shwartsman
892fa99c6f
- prefetch hint should be NOP when use in register mode
...
- #GP when trying to set reserved bits of CR4_HI in 64-bit mode
- #GP when trying to set reserved bits of EFER MSR
- clear upper part of RSI/RDI when executing rep instructions with 32-bit asize
even if no repeat iterations were executed (because of RCX=0 for example)
- write SYSENTER_EIP_MSR and SYSENTER_ESP_MSR as 64-bit when x86_64 supported
- set MSR_FMASK reset value
- MSR_FMASK should be 32-bit only
- check for fetch permissions when doing ITLB lookup
- #GP when trying to write non-canonical address to MSR_CSTAR or MSR_LSTAR
- correct repeat instructions timing
- mark TSS busy in TR after it is loaded
2008-04-16 16:44:06 +00:00
Stanislav Shwartsman
419dc57dbd
Complete MASKMOVDQU decoding fix
2008-04-16 05:56:55 +00:00
Stanislav Shwartsman
4f3f8608f7
Fixed MASKMOVDQU instruction decoding
2008-04-16 05:41:43 +00:00
Stanislav Shwartsman
fe59e0ae6a
FIxed comment in fetchdecode
2008-04-06 18:31:10 +00:00
Stanislav Shwartsman
1bdddc1f78
Split SHRD/SHLD instructions
2008-04-05 19:08:01 +00:00
Stanislav Shwartsman
5826e2843a
Inline pop/push functions
...
Store only single byte of opcode in b1() - speedup shift instructions
Code cleanups
2008-04-05 17:51:55 +00:00
Stanislav Shwartsman
2aaafa76a2
Reorganize fetchdecode tables with another level of redirection - a leap toward future improvements
...
Currently no speedup and no slowdown - about the same results on my Bochs benchmarking
A lot of code reorganization in fetchdecode
2008-04-04 22:39:45 +00:00
Stanislav Shwartsman
62e3728591
preparations for future optimizations - not necessary speedupo now
2008-04-03 17:56:59 +00:00
Stanislav Shwartsman
3f2487a0af
Enabled tracing cross repeated instructions
2008-03-31 18:53:08 +00:00
Stanislav Shwartsman
255d512e29
Organize bxInstruction fields differently
2008-03-31 17:33:34 +00:00
Stanislav Shwartsman
14ff07b482
Small code cleanup
2008-03-29 09:58:23 +00:00
Stanislav Shwartsman
e48b398bee
Add NIL register and simplify more BxResolve work
2008-03-29 09:34:35 +00:00
