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363 Commits

Author SHA1 Message Date
Stanislav Shwartsman
e79185b0a0 refactor memtype methods 2015-03-02 20:51:59 +00:00
Stanislav Shwartsman
36f7bf0ba6 fixed ept memtype printout 2015-03-01 21:04:34 +00:00
Stanislav Shwartsman
8134dc67af supporting memory type provided by page tables with PCD,PWT and PAT bits 
TODO: support memory type with EPT
TODO: support memory type for intermediate page table accesses
TODO: check what happens when PAT is not enabled in CPU configuration
 2015-03-01 20:55:23 +00:00
Stanislav Shwartsman
53041981f7 supply PAT required memory type bits through new combined access interface 2015-02-28 14:06:04 +00:00
Stanislav Shwartsman
25b02dac4b code reorg before PAT memory type support 2015-02-28 14:01:11 +00:00
Stanislav Shwartsman
1e1c893041 introduce new 64bit packed register type and implement pat/mtrr and mmx registers through it 2015-02-23 21:17:33 +00:00
Stanislav Shwartsman
2bad0d0d12 fixed link error with debugger enabled, small speed optimization 2015-02-23 19:55:55 +00:00
Stanislav Shwartsman
0917d12e8b memory type report for physical accesses and RMW acccesses. todo: consider also pat 2015-02-22 21:26:26 +00:00
Stanislav Shwartsman
7a3e340e6d implement memory type calculation by mtrr. todo: memory type from page tables 2015-02-20 21:50:59 +00:00
Stanislav Shwartsman
e16c6eb30c preparations and interface definition for memory type support 2015-02-19 20:23:08 +00:00
Volker Ruppert
2ec57b8a6b Fixed some more C++11 warnings. 2014-12-18 17:52:40 +00:00
Stanislav Shwartsman
8d1e3b2ac1 Added statistics collection infrastructure in Bochs and 
implemented important CPU statistics which were used for Bochs CPU model performance analysis.
old statistics code from paging.cc and cpu.cc is replaced with new infrastructure.

In order to enale statitics collection in Bochs CPU:

- Enable statistics @ compilation time in cpu/cpustats.h
- Dump statistics periodically by adding -dumpstats N into Bochs command line
 2014-10-14 15:59:10 +00:00
Stanislav Shwartsman
5eb781e45f cleanup after cpu features interface rework 2014-08-31 19:22:41 +00:00
Stanislav Shwartsman
816f5cc2d7 fixed massive code duplication 2014-07-03 06:40:42 +00:00
Stanislav Shwartsman
776cabf4fe move canonical check of high part of page split access to another function to fix code duplication 2013-12-21 21:56:55 +00:00
Stanislav Shwartsman
a85a9081b7 use shorter opcode names in the debug prints (skip the BX_IA_ prefix) 2013-12-02 20:06:59 +00:00
Stanislav Shwartsman
d082c6a0f9 implemented avx-512 masked load instructions 2013-11-30 18:37:25 +00:00
Stanislav Shwartsman
2357dc5ccc Fixed number of invocations of the BX_INSTR_LIN_ACCESS instrumentation callback in cpu/access32.cc, cpu/access64.cc and cpu/paging.cc specify the BX_READ memory access type where BX_RW really applies. 
SF Patch #1335 by Mateusz Jurczyk
 2013-07-24 18:54:18 +00:00
Stanislav Shwartsman
53d14c01b5 correctly signal bit 12 (nmi unblocking by iret) in vmx interruption info. todo: find how to implement it clean way 2013-03-06 21:11:23 +00:00
Stanislav Shwartsman
40669115e1 use different formatter for printing phy address in paging dbg messages 2013-02-14 19:30:59 +00:00
Stanislav Shwartsman
64df073617 implemented virtualization exception feature 2013-01-28 16:30:25 +00:00
Stanislav Shwartsman
d38fce8218 preparation for future extension in translate_linear - I would like to return data to caller through tlbEntry 2013-01-27 19:27:30 +00:00
Stanislav Shwartsman
4bed791ccb Added year 2013 to Copyright in all files already modified in new year 2013-01-19 20:45:03 +00:00
Stanislav Shwartsman
05d36f0acc fixed performance bug in smap/smep fix - tlb never had user executable page permission 2013-01-19 20:14:44 +00:00
Stanislav Shwartsman
eda28b95f4 unfortunately this change is rquired to make SMAP and SMEP features to work. 
I observed ~5% emulation slowdown ... thinking about possible mitigations

this fixes TLB issue with SMAP and SMEP features.
these features introduce a new behavior when page can be inaccessible by System (CPL=0).
Current behavior is accessBits was not supporting it but legacy (from Bochs 2.3.6) was.
The wrong behavior can be observed if user access a user page and system access the same page later.
user access is fine and pass SMEP/SMA checks and stores the translation in TLB.
the system access will hit the TLB and nobody could detect that system cannot access that page.
 2013-01-16 17:28:20 +00:00
Stanislav Shwartsman
574b69c81e fixed MSDEV warnings 2012-11-27 15:40:45 +00:00
Stanislav Shwartsman
8a01ee1661 implemented SVM decode assists. some is still missing - coming soon 2012-11-02 07:46:50 +00:00
Stanislav Shwartsman
744001e35e Implemented VMX APIC Registers Virtualization and VMX Virtual Interrupt Delivery emulation 
Bugfix: VMX: VmEntry should do TPR Virtualization (TPR Shadow + APIC Access Virtualization case is affected) and even could possibly cause TPR Threshold VMEXIT
 2012-10-26 18:43:53 +00:00
Stanislav Shwartsman
2f3c7ff8e4 implemented SMAP (Supervisor Mode Access Protection) from [Intel Architecture Instruction Set Extensions Programming Reference] rev14 
fixed enabling of ADX extensions in generic CPUID when enabled through .bochsrc

Small code cleanups on the way to implementation of APIC Registers Virtualization features disclosed in recent Intel SDM rev043
 2012-09-10 15:22:26 +00:00
Stanislav Shwartsman
e0729e32b8 fixed bug 3548108 VMEXIT instruction length Not always getting updated 2012-07-26 16:03:26 +00:00
Stanislav Shwartsman
3415f7bb0f add XD bit to page attributes print 2012-06-28 10:59:30 +00:00
Stanislav Shwartsman
515d8b5c25 add new instrumentation callbacks for physical memory access from CPU 2012-06-18 11:41:26 +00:00
Stanislav Shwartsman
171d400bd8 GATHER: update gather mask handling to match latest Intel SDM definition 
Fixes in x86 HW breakpoint handling
 2012-06-06 14:01:45 +00:00
Stanislav Shwartsman
f528290652 fixed bug EPT Access Dirty support 2012-05-27 19:17:13 +00:00
Stanislav Shwartsman
39c14ef0d1 Implemented EPT A/D extensions support. 
Bochs is fully aligned with the latest published revision of
Intel Architecture Manual (revision 043) now.
 2012-05-02 18:11:39 +00:00
Stanislav Shwartsman
279c61dc67 updated + fixed instrumentation example for instr histogram, code cleanup in the cpu 2012-03-28 21:11:19 +00:00
Stanislav Shwartsman
3ca29cbdf3 stack direct access optimization - 5% emu speedup to all 32-bit guests, for 64-bit guests speedup is less because they have less stack accesses 2012-03-25 11:54:32 +00:00
Stanislav Shwartsman
b5a33e82ac fixed a lot of code duplication in debugging/instrumentation of mem access 2012-03-20 18:26:04 +00:00
Stanislav Shwartsman
c52d97cb7f fixed comments in paging.cc 2012-02-28 22:39:33 +00:00
Stanislav Shwartsman
f48317affc SVM: Added EXITINFO2 write on VMEXIT (missed in prev commit) 
Added phenom_8650_toliman <AMD Phenom X3 8650 (Toliman)> comment into .bochsrc example with all other supported CPU configs.
Added missed SVM definitions into Toliman CPUDB module
 2012-02-19 20:15:23 +00:00
Stanislav Shwartsman
92376fb693 svm updates 2012-02-19 12:16:58 +00:00
Stanislav Shwartsman
c2670b40d5 small cleanup in paging code 2012-02-15 19:49:35 +00:00
Stanislav Shwartsman
bb7a648d91 Major commit ! 
------------

Implemented SVN nested paging support - the Virtual Box boots perfectly with Nested Paging guest !
A lot of code duplication was added for now - major cleanup will follow later.

! Added AMD Phenom X3 8650 (Toliman) configuration to the CPUDB - this configuration has Nested Paging enabled.

Some CPUID modules rework done to enable Toliman configuration.

Ckean up 'executable' attribute from all CPU source files.
 2012-02-13 23:29:01 +00:00
Stanislav Shwartsman
813fe4e6b9 reduce code duplication - continue preparing for nested paging implementation 2012-02-13 20:06:04 +00:00
Stanislav Shwartsman
4d0a5c1b07 - VMX: EPT misconfiguration should always take priority above EPT permissions violation (translate_guest_physical corner case bug) 
- VMX: EPT reserved bits set should cause EPT misconfiguration and not EPT violation
- VMX: EPT walk for guest CR3 address should be considered as 'page walk'
 2012-02-12 21:30:22 +00:00
Stanislav Shwartsman
0b5f798af1 re-commit changes from SVN rev11026 which were accidentially undo'ed by last Volker's commit 2012-02-12 19:13:57 +00:00
Volker Ruppert
de94b08a1a - class bx_list_c now contains a chained list of parameters. Removed the now 
obsolete maxsize parameter from all lists.
 2012-02-12 18:43:20 +00:00
Stanislav Shwartsman
855d2adece cleanups in paging code 2012-02-12 16:09:35 +00:00
Stanislav Shwartsman
fa182e96b5 for future nested paging: under NP PDPTR CACHE will contain NP PDPTR entries 2012-02-10 20:39:46 +00:00
Stanislav Shwartsman
457c56c822 fixup for EPT paging 2012-01-22 18:39:15 +00:00
Stanislav Shwartsman
fc6712e3a3 undo part of prev paging commit 2012-01-19 20:01:32 +00:00
Stanislav Shwartsman
12afed23a1 small fix and cleanups in paging code 2012-01-19 06:38:22 +00:00
Stanislav Shwartsman
9461797886 added extra param to debugger phy access callback + cleanup in vmexit functions 2012-01-17 21:50:15 +00:00
Stanislav Shwartsman
f4b49633d4 paging code rework (cont) 2012-01-17 18:20:55 +00:00
Stanislav Shwartsman
0d64a6cb92 fixed paging bug in previous commit 2012-01-16 15:26:25 +00:00
Stanislav Shwartsman
7d641450ec remove param from check_entry_PAE function - it is always the same for all calls 2012-01-15 20:25:39 +00:00
Stanislav Shwartsman
c7cb99787e rework in paging code before nested paging implementation for SVM - step 2 
optimize TLB flush code
 2012-01-15 19:38:00 +00:00
Stanislav Shwartsman
4db23355cd rework in paging code before nested paging implementation for SVM - step 1 2012-01-15 17:54:13 +00:00
Stanislav Shwartsman
edfff5bf44 fixed VMX+EPT VirtualBox failures 2012-01-06 10:30:07 +00:00
Stanislav Shwartsman
e2ff4bc6d4 clear exitinfo1/2 fields in SVM on VMENTER 2012-01-05 22:23:05 +00:00
Stanislav Shwartsman
0a14f08f16 completing SVM coding, missed - CPUID, extended APIC 2011-12-28 16:12:28 +00:00
Stanislav Shwartsman
7f5f917a34 more SVM implementation 2011-12-27 19:42:11 +00:00
Stanislav Shwartsman
75bda1d5cd implemented SVM emulation support for Bochs (incomplete yet) 
I am merging the code in order to start making shortcuts between VMX emulation and SVM emulation.
Of course SVM emulation is incomplete, completely untested and not expected to work.
But someone could already take a look one the code and give some suggestions.

Also looking for anybody with existing SVM kernels - as simple as possible - for testing.

Status:
 - exceptions intercept is not implemented yet
 - IO intercept is not implemented yet
 - MSR intercept is not implemented yet
 - virtual interrupts are not implemented yet
 - CPUID is not implemented yet

No advanced SVM featurez planned - I am implementing the very basic 'Pacifica' document from 2005 using QEMU code as reference.
 2011-12-25 19:35:29 +00:00
Stanislav Shwartsman
0547c8823e compilation w/o x86-64 2011-09-26 19:48:58 +00:00
Stanislav Shwartsman
12ad45395b enable Penryn VMX capabilities with VMX=1, VMX=2 is required for EPT and heavier stuff 2011-09-26 19:36:20 +00:00
Stanislav Shwartsman
fa930961c2 small optimization 2011-08-23 21:25:34 +00:00
Stanislav Shwartsman
f15bc6cf75 support for NX outside of x86-64. 
required for Intel Yonah processor which is another interesting CPUID to be added
also found Via C7 CPUID, looking for the way to add it too
 2011-08-10 22:04:33 +00:00
Stanislav Shwartsman
0171324877 small favor to VMX OFF for code that compiled with VMX ON 
avoid function call when not in vmx guest.
 2011-08-09 20:50:51 +00:00
Stanislav Shwartsman
17a94fc58e warning fixes 2011-08-09 18:00:19 +00:00
Stanislav Shwartsman
d11114ac19 Patch for emulating target with larger memory than host has available by Gary Cameron. 
The patch was posted in mailing list at Thu 6/16/2011.

Desription for CHANGES:

- Memory
  - Added new configure option which enables RAM file backing for large guest
    memory with a smaller amount host memory, without causing a panic when
    host memory is exhausted (patch by Gary Cameron). To enable configure with
        --enable-large-ramfile option.
 2011-07-22 17:46:06 +00:00
Stanislav Shwartsman
b4118fcbfe correct natural width VMX field read/write len 2011-07-21 20:58:54 +00:00
Stanislav Shwartsman
f81e47cca2 it is better to handle A20 in paging already 2011-07-18 20:22:59 +00:00
Stanislav Shwartsman
002c86660a reword all the CPU code in preparation for future CPU speedup implementation. 
Bochs emulation can be another 10-15% faster using technique described in paper
"Fast Microcode Interpretation with Transactional Commit/Abort"
http://amas-bt.cs.virginia.edu/2011proceedings/amasbt2011-p3.pdf
 2011-07-06 20:01:18 +00:00
Stanislav Shwartsman
90c4a74362 typo fix 2011-06-28 16:29:11 +00:00
Stanislav Shwartsman
08ba847ce4 fix bug inserted with prev commit + cleanup 2011-06-28 16:04:40 +00:00
Stanislav Shwartsman
7e57d95364 Fix wrong address translation in debugger 2011-06-24 13:05:36 +00:00
Stanislav Shwartsman
acf2175d6d paging small change 2011-06-03 20:50:55 +00:00
Stanislav Shwartsman
04e9254e2c AMD released new Vol4: 128 and 256 bit vector instructions, dropped SSE4A 2011-05-30 20:15:50 +00:00
Stanislav Shwartsman
0de8b08f24 fixed too few arguments for format warning 2011-05-29 20:09:31 +00:00
Stanislav Shwartsman
ee3f9e36cb Implemented Supervisor Mode Execution Protection (SMEP) 2011-05-29 16:28:26 +00:00
Stanislav Shwartsman
75ec0f835e small bug fix for 32-bit linear addr wrap 2011-05-27 08:50:38 +00:00
Stanislav Shwartsman
a02d8cfe67 cleanups, simplications, copyright updates 2011-04-23 20:39:27 +00:00
Stanislav Shwartsman
6e79fdfb1e optimize data hw breakpoint 2011-04-09 05:12:28 +00:00
Stanislav Shwartsman
7d80a6ebe0 Adding Id and Rev property to all files 2011-02-24 21:54:04 +00:00
Stanislav Shwartsman
d8a2736d72 VMX pw loads should ask for RD perm 2011-02-19 08:31:05 +00:00
Stanislav Shwartsman
b5ebe5865e Fixes for incoming bug report, missed changes in CVS, repository fixups and etc 2011-02-11 09:56:23 +00:00
Stanislav Shwartsman
9aa503cb9d fixed warnings for win64 compilation 2010-11-23 14:59:36 +00:00
Stanislav Shwartsman
6d089dd238 changed CPUID constants to defines 2010-10-07 16:39:31 +00:00
Stanislav Shwartsman
95df639614 compilation fix 2010-05-25 18:52:01 +00:00
Stanislav Shwartsman
05bbbb1a2c compilation fix 2010-05-16 05:23:18 +00:00
Stanislav Shwartsman
1c47847e23 Show more fields for verbose debugger 'page'command 2010-05-05 20:10:15 +00:00
Stanislav Shwartsman
9a43a89a61 verbose page command from the debugger 2010-05-04 20:16:38 +00:00
Stanislav Shwartsman
aa76181208 Fixed debug translation 2010-05-04 19:02:51 +00:00
Stanislav Shwartsman
1c2fa8cd0c move 1G_pages support to runtime option 2010-04-24 09:36:04 +00:00
Stanislav Shwartsman
77f8857ddb Fixed dbg_linear2phy function for legacy PAE 2010-04-14 15:41:57 +00:00
Stanislav Shwartsman
df07dab80f verbose phy mem access tracing 2010-04-13 17:56:50 +00:00
Stanislav Shwartsman
6e1204cb84 Merged X2APIC + X2APIC virtualization 2010-04-08 15:50:39 +00:00
Stanislav Shwartsman
df7db31fb4 EPT + VPID - VMXx2 support 2010-04-07 17:12:17 +00:00
Stanislav Shwartsman
c94e72d4d3 make lpf_mask smaller 2010-04-07 14:38:53 +00:00
Stanislav Shwartsman
10505dca81 PDPTR checks fix 2010-04-06 19:26:03 +00:00