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verbose phy mem access tracing

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This commit is contained in:
Stanislav Shwartsman 2010-04-13 17:56:50 +00:00
parent 1a2c73bba3
commit df07dab80f
7 changed files with 108 additions and 56 deletions
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1
bochs/CHANGES
View File

@ -62,6 +62,7 @@ Detailed change log :
- Internal Debugger
- Introduced range read/write physical watchpoints
- Allow reloading of segment registers from internal debugger
- Improved verbose physical memory access tracing
- BIOS
- Fix MTRR configuration (prevented boot of modern Linux kernels)

23
bochs/bochs.h
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: bochs.h,v 1.252 2010-02-11 22:12:17 sshwarts Exp $
// $Id: bochs.h,v 1.253 2010-04-13 17:56:50 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2009 The Bochs Project
@ -451,6 +451,27 @@ BOCHSAPI extern bx_debug_t bx_dbg;
#define BX_EXECUTE 2
#define BX_RW 3
// to be used in concatenation with BX_READ/BX_WRITE/BX_EXECUTE/BX_RW
#define BX_PDPTR0_ACCESS 0x010
#define BX_PDPTR1_ACCESS 0x020
#define BX_PDPTR2_ACCESS 0x030
#define BX_PDPTR3_ACCESS 0x040
#define BX_PTE_ACCESS 0x050
#define BX_PDE_ACCESS 0x060
#define BX_PDPTE_ACCESS 0x070
#define BX_PML4E_ACCESS 0x080
#define BX_EPT_PTE_ACCESS 0x090
#define BX_EPT_PDE_ACCESS 0x0a0
#define BX_EPT_PDPTE_ACCESS 0x0b0
#define BX_EPT_PML4E_ACCESS 0x0c0
#define BX_VMCS_ACCESS 0x0d0
#define BX_VMX_MSR_BITMAP_ACCESS 0x0e0
#define BX_VMX_IO_BITMAP_ACCESS 0x0f0
#define BX_VMX_LOAD_MSR_ACCESS 0x100
#define BX_VMX_STORE_MSR_ACCESS 0x110
#define BX_VMX_VTPR_ACCESS 0x120
#define BX_SMRAM_ACCESS 0x130
// types of reset
#define BX_RESET_SOFTWARE 10
#define BX_RESET_HARDWARE 11

32
bochs/bx_debug/dbg_main.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: dbg_main.cc,v 1.235 2010-04-03 05:59:07 sshwarts Exp $
// $Id: dbg_main.cc,v 1.236 2010-04-13 17:56:50 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2009 The Bochs Project
@ -612,6 +612,31 @@ void bx_dbg_phy_memory_access(unsigned cpu, bx_phy_address phy, unsigned len, un
if (! BX_CPU(cpu)->trace_mem)
return;
unsigned access = rw >> 4;
static const char *access_string[] = {
"",
"PDPTR0",
"PDPTR1",
"PDPTR2",
"PDPTR3",
"PTE",
"PDE",
"PDPTE",
"PML4E",
"EPT PTE",
"EPT PDE",
"EPT PDPTE",
"EPT PML4E",
"VMCS",
"VMX MSR BITMAP",
"VMX I/O BITMAP",
"VMX LDMSR",
"VMX STMSR",
"VMX VTPR",
"SMRAM"
};
bx_bool write = rw & 1;
dbg_printf("[CPU%d %s]: PHY 0x" FMT_PHY_ADDRX " (len=%d)",
@ -644,7 +669,10 @@ void bx_dbg_phy_memory_access(unsigned cpu, bx_phy_address phy, unsigned len, un
}
#endif
dbg_printf("\n");
if (access != 0)
dbg_printf("\t; %s\n", access_string[access]);
else
dbg_printf("\n");
}
void bx_dbg_exit(int code)

54
bochs/cpu/paging.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: paging.cc,v 1.217 2010-04-08 15:50:39 sshwarts Exp $
// $Id: paging.cc,v 1.218 2010-04-13 17:56:50 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2010 The Bochs Project
@ -669,7 +669,7 @@ bx_phy_address BX_CPU_C::translate_linear_long_mode(bx_address laddr, Bit32u &lp
}
#endif
access_read_physical(entry_addr[leaf], 8, &entry[leaf]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[leaf], 8, BX_READ, (Bit8u*)(&entry[leaf]));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[leaf], 8, (BX_PTE_ACCESS + (leaf<<4)) | BX_READ, (Bit8u*)(&entry[leaf]));
Bit64u curr_entry = entry[leaf];
int fault = check_entry_PAE(bx_paging_level[leaf], curr_entry, PAGING_PAE_RESERVED_BITS, rw, &nx_fault);
@ -730,7 +730,8 @@ bx_phy_address BX_CPU_C::translate_linear_long_mode(bx_address laddr, Bit32u &lp
if (!(entry[level] & 0x20)) {
entry[level] |= 0x20;
access_write_physical(entry_addr[level], 8, &entry[level]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[level], 8, BX_WRITE, (Bit8u*)(&entry[level]));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[level], 8,
(BX_PTE_ACCESS + (level<<4)) | BX_WRITE, (Bit8u*)(&entry[level]));
}
}
@ -738,7 +739,8 @@ bx_phy_address BX_CPU_C::translate_linear_long_mode(bx_address laddr, Bit32u &lp
if (!(entry[leaf] & 0x20) || (isWrite && !(entry[leaf] & 0x40))) {
entry[leaf] |= (0x20 | (isWrite<<6)); // Update A and possibly D bits
access_write_physical(entry_addr[leaf], 8, &entry[leaf]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[leaf], 8, BX_WRITE, (Bit8u*)(&entry[leaf]));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[leaf], 8,
(BX_PTE_ACCESS + (leaf<<4)) | BX_WRITE, (Bit8u*)(&entry[leaf]));
}
return ppf;
@ -778,7 +780,9 @@ bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::CheckPDPTR(bx_phy_address cr3_val)
// read and check PDPTE entries
bx_phy_address pdpe_entry_addr = (bx_phy_address) (cr3_val | (n << 3));
access_read_physical(pdpe_entry_addr, 8, &(pdptr[n]));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pdpe_entry_addr, 8, BX_READ, (Bit8u*) &(pdptr[n]));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pdpe_entry_addr, 8,
(BX_PDPTR0_ACCESS + (n<<4)) | BX_READ, (Bit8u*) &(pdptr[n]));
if (pdptr[n] & 0x1) {
if (pdptr[n] & PAGING_PAE_PDPTE_RESERVED_BITS) return 0;
}
@ -823,7 +827,7 @@ bx_phy_address BX_CPU_C::translate_linear_PAE(bx_address laddr, Bit32u &lpf_mask
#endif
if (! BX_CPU_THIS_PTR PDPTR_CACHE.valid) {
BX_ERROR(("PDPTR_CACHE not valid !"));
BX_PANIC(("PDPTR_CACHE not valid !"));
if (! CheckPDPTR(BX_CPU_THIS_PTR cr3)) {
BX_ERROR(("translate_linear_PAE(): PDPTR check failed !"));
exception(BX_GP_EXCEPTION, 0);
@ -845,7 +849,7 @@ bx_phy_address BX_CPU_C::translate_linear_PAE(bx_address laddr, Bit32u &lpf_mask
}
#endif
access_read_physical(entry_addr[BX_LEVEL_PDE], 8, &entry[BX_LEVEL_PDE]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[BX_LEVEL_PDE], 8, BX_READ, (Bit8u*)(&entry[BX_LEVEL_PDE]));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[BX_LEVEL_PDE], 8, BX_PDE_ACCESS | BX_READ, (Bit8u*)(&entry[BX_LEVEL_PDE]));
fault = check_entry_PAE("PDE", entry[BX_LEVEL_PDE], PAGING_PAE_RESERVED_BITS, rw, &nx_fault);
if (fault >= 0)
@ -875,7 +879,7 @@ bx_phy_address BX_CPU_C::translate_linear_PAE(bx_address laddr, Bit32u &lpf_mask
}
#endif
access_read_physical(entry_addr[BX_LEVEL_PTE], 8, &entry[BX_LEVEL_PTE]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[BX_LEVEL_PTE], 8, BX_READ, (Bit8u*)(&entry[BX_LEVEL_PTE]));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[BX_LEVEL_PTE], 8, BX_PTE_ACCESS | BX_READ, (Bit8u*)(&entry[BX_LEVEL_PTE]));
fault = check_entry_PAE("PTE", entry[BX_LEVEL_PTE], PAGING_PAE_RESERVED_BITS, rw, &nx_fault);
if (fault >= 0)
@ -905,7 +909,8 @@ bx_phy_address BX_CPU_C::translate_linear_PAE(bx_address laddr, Bit32u &lpf_mask
if (!(entry[BX_LEVEL_PDE] & 0x20)) {
entry[BX_LEVEL_PDE] |= 0x20;
access_write_physical(entry_addr[BX_LEVEL_PDE], 8, &entry[BX_LEVEL_PDE]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[BX_LEVEL_PDE], 8, BX_WRITE, (Bit8u*)(&entry[BX_LEVEL_PDE]));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[BX_LEVEL_PDE], 8,
(BX_PDE_ACCESS | BX_WRITE), (Bit8u*)(&entry[BX_LEVEL_PDE]));
}
}
@ -913,7 +918,8 @@ bx_phy_address BX_CPU_C::translate_linear_PAE(bx_address laddr, Bit32u &lpf_mask
if (!(entry[leaf] & 0x20) || (isWrite && !(entry[leaf] & 0x40))) {
entry[leaf] |= (0x20 | (isWrite<<6)); // Update A and possibly D bits
access_write_physical(entry_addr[leaf], 8, &entry[leaf]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[leaf], 8, BX_WRITE, (Bit8u*)(&entry[leaf]));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[leaf], 8,
(BX_PTE_ACCESS + (leaf<<4)) | BX_WRITE, (Bit8u*)(&entry[leaf]));
}
return ppf;
@ -1001,7 +1007,7 @@ bx_phy_address BX_CPU_C::translate_linear(bx_address laddr, unsigned curr_pl, un
}
#endif
access_read_physical(pde_addr, 4, &pde);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pde_addr, 4, BX_READ, (Bit8u*)(&pde));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pde_addr, 4, BX_PDE_ACCESS | BX_READ, (Bit8u*)(&pde));
if (!(pde & 0x1)) {
BX_DEBUG(("PDE: entry not present"));
@ -1036,7 +1042,7 @@ bx_phy_address BX_CPU_C::translate_linear(bx_address laddr, unsigned curr_pl, un
if (!(pde & 0x20) || (isWrite && !(pde & 0x40))) {
pde |= (0x20 | (isWrite<<6)); // Update A and possibly D bits
access_write_physical(pde_addr, 4, &pde);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pde_addr, 4, BX_WRITE, (Bit8u*)(&pde));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pde_addr, 4, BX_PDE_ACCESS | BX_WRITE, (Bit8u*)(&pde));
}
// make up the physical frame number
@ -1058,7 +1064,7 @@ bx_phy_address BX_CPU_C::translate_linear(bx_address laddr, unsigned curr_pl, un
}
#endif
access_read_physical(pte_addr, 4, &pte);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pte_addr, 4, BX_READ, (Bit8u*)(&pte));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pte_addr, 4, BX_PTE_ACCESS | BX_READ, (Bit8u*)(&pte));
if (!(pte & 0x1)) {
BX_DEBUG(("PTE: entry not present"));
@ -1093,14 +1099,14 @@ bx_phy_address BX_CPU_C::translate_linear(bx_address laddr, unsigned curr_pl, un
if (!(pde & 0x20)) {
pde |= 0x20;
access_write_physical(pde_addr, 4, &pde);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pde_addr, 4, BX_WRITE, (Bit8u*)(&pde));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pde_addr, 4, BX_PDE_ACCESS | BX_WRITE, (Bit8u*)(&pde));
}
// Update PTE A/D bits if needed.
if (!(pte & 0x20) || (isWrite && !(pte & 0x40))) {
pte |= (0x20 | (isWrite<<6)); // Update A and possibly D bits
access_write_physical(pte_addr, 4, &pte);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pte_addr, 4, BX_WRITE, (Bit8u*)(&pte));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pte_addr, 4, BX_PTE_ACCESS | BX_WRITE, (Bit8u*)(&pte));
}
// Make up the physical page frame address.
@ -1213,7 +1219,8 @@ bx_phy_address BX_CPU_C::translate_guest_physical(bx_phy_address guest_paddr, bx
for (leaf = BX_LEVEL_PML4;; --leaf) {
entry_addr[leaf] = pbase + ((guest_paddr >> (9 + 9*leaf)) & 0xff8);
access_read_physical(entry_addr[leaf], 8, &entry[leaf]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[leaf], 8, BX_READ, (Bit8u*)(&entry[leaf]));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[leaf], 8,
(BX_EPT_PTE_ACCESS + (leaf<<4)) | BX_READ, (Bit8u*)(&entry[leaf]));
Bit64u curr_entry = entry[leaf];
Bit32u curr_access_mask = curr_entry & 0x7;
@ -1336,21 +1343,16 @@ bx_bool BX_CPU_C::dbg_translate_guest_physical(bx_phy_address guest_paddr, bx_ph
pt_address = bx_phy_address(pte & BX_CONST64(0x000ffffffffff000));
if (level == BX_LEVEL_PTE) break;
if (pte & 0x80) {
if (level == BX_LEVEL_PDE) { // 2M page
if (level > (BX_LEVEL_PDE + BX_SUPPORT_1G_PAGES))
return 0;
pt_address &= BX_CONST64(0x000fffffffffe000);
if (pt_address & offset_mask) return 0;
break;
}
#if BX_SUPPORT_1G_PAGES
if (level == BX_LEVEL_PDPE) { // 1G page
pt_address &= BX_CONST64(0x000fffffffffe000);
if (pt_address & offset_mask) return 0;
break;
}
#endif
if (level != BX_LEVEL_PTE) return 0;
}
}
*phy = pt_address + (bx_phy_address)(guest_paddr & offset_mask);

8
bochs/cpu/smm.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: smm.cc,v 1.70 2010-04-07 14:49:18 sshwarts Exp $
// $Id: smm.cc,v 1.71 2010-04-13 17:56:50 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2006-2009 Stanislav Shwartsman
@ -100,7 +100,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::RSM(bxInstruction_c *i)
for(n=0;n<SMM_SAVE_STATE_MAP_SIZE;n++) {
base -= 4;
access_read_physical(base, 4, &saved_state[n]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, base, 4, BX_READ, (Bit8u*)(&saved_state[n]));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, base, 4, BX_SMRAM_ACCESS | BX_READ, (Bit8u*)(&saved_state[n]));
}
BX_CPU_THIS_PTR in_smm = 0;
@ -158,14 +158,14 @@ void BX_CPU_C::enter_system_management_mode(void)
// reset reserved bits
for(n=0;n<SMM_SAVE_STATE_MAP_SIZE;n++) saved_state[n] = 0;
// prepare CPU state to be saved in the SMRAM
BX_CPU_THIS_PTR smram_save_state(saved_state);
smram_save_state(saved_state);
bx_phy_address base = BX_CPU_THIS_PTR smbase + 0x10000;
// could be optimized with reading of only non-reserved bytes
for(n=0;n<SMM_SAVE_STATE_MAP_SIZE;n++) {
base -= 4;
access_write_physical(base, 4, &saved_state[n]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, base, 4, BX_WRITE, (Bit8u*)(&saved_state[n]));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, base, 4, BX_SMRAM_ACCESS | BX_WRITE, (Bit8u*)(&saved_state[n]));
}
BX_CPU_THIS_PTR setEFlags(0x2); // Bit1 is always set

12
bochs/cpu/vmexit.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: vmexit.cc,v 1.25 2010-04-08 15:50:39 sshwarts Exp $
// $Id: vmexit.cc,v 1.26 2010-04-13 17:56:50 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2009-2010 Stanislav Shwartsman
@ -372,7 +372,7 @@ void BX_CPP_AttrRegparmN(3) BX_CPU_C::VMexit_MSR(bxInstruction_c *i, unsigned op
// check MSR-HI bitmaps
bx_phy_address pAddr = vm->msr_bitmap_addr + (msr >> 3) + 1024 + ((op == VMX_VMEXIT_RDMSR) ? 0 : 2048);
access_read_physical(pAddr, 1, &field);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 1, BX_READ, &field);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 1, BX_VMX_MSR_BITMAP_ACCESS | BX_READ, &field);
if (field & (1 << (msr & 7)))
vmexit = 1;
}
@ -383,7 +383,7 @@ void BX_CPP_AttrRegparmN(3) BX_CPU_C::VMexit_MSR(bxInstruction_c *i, unsigned op
// check MSR-LO bitmaps
bx_phy_address pAddr = vm->msr_bitmap_addr + (msr >> 3) + ((op == VMX_VMEXIT_RDMSR) ? 0 : 2048);
access_read_physical(pAddr, 1, &field);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 1, BX_READ, &field);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 1, BX_VMX_MSR_BITMAP_ACCESS | BX_READ, &field);
if (field & (1 << (msr & 7)))
vmexit = 1;
}
@ -416,7 +416,7 @@ void BX_CPP_AttrRegparmN(3) BX_CPU_C::VMexit_IO(bxInstruction_c *i, unsigned por
bx_phy_address pAddr = BX_CPU_THIS_PTR vmcs.io_bitmap_addr[(port >> 15) & 1] + ((port & 0x7fff) >> 3);
Bit16u bitmap;
access_read_physical(pAddr, 2, (Bit8u*) &bitmap);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 2, BX_READ, (Bit8u*) &bitmap);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 2, BX_VMX_IO_BITMAP_ACCESS | BX_READ, (Bit8u*) &bitmap);
unsigned mask = ((1 << len) - 1) << (port & 7);
if (bitmap & mask) vmexit = 1;
@ -684,7 +684,7 @@ Bit32u BX_CPU_C::VMX_Read_VTPR(void)
bx_phy_address pAddr = BX_CPU_THIS_PTR vmcs.virtual_apic_page_addr + 0x80;
Bit32u vtpr;
access_read_physical(pAddr, 4, (Bit8u*)(&vtpr));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 4, BX_READ, (Bit8u*)(&vtpr));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 4, BX_VMX_VTPR_ACCESS | BX_READ, (Bit8u*)(&vtpr));
return vtpr;
}
@ -695,7 +695,7 @@ void BX_CPU_C::VMX_Write_VTPR(Bit8u vtpr)
Bit32u field32 = vtpr;
access_write_physical(pAddr, 4, (Bit8u*)(&field32));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 4, BX_WRITE, (Bit8u*)(&field32));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 4, BX_VMX_VTPR_ACCESS | BX_WRITE, (Bit8u*)(&field32));
Bit8u tpr_shadow = vtpr >> 4;
if (tpr_shadow < vm->vm_tpr_threshold) {

34
bochs/cpu/vmx.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: vmx.cc,v 1.64 2010-04-09 15:19:14 sshwarts Exp $
// $Id: vmx.cc,v 1.65 2010-04-13 17:56:50 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2009-2010 Stanislav Shwartsman
@ -107,7 +107,7 @@ Bit16u BX_CPU_C::VMread16(unsigned encoding)
access_read_physical(pAddr, 2, (Bit8u*)(&field));
}
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 2, BX_READ, (Bit8u*)(&field));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 2, BX_VMCS_ACCESS | BX_READ, (Bit8u*)(&field));
return field;
}
@ -131,7 +131,7 @@ void BX_CPU_C::VMwrite16(unsigned encoding, Bit16u val_16)
access_write_physical(pAddr, 2, (Bit8u*)(&val_16));
}
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 2, BX_WRITE, (Bit8u*)(&val_16));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 2, BX_VMCS_ACCESS | BX_WRITE, (Bit8u*)(&val_16));
}
Bit32u BX_CPU_C::VMread32(unsigned encoding)
@ -151,7 +151,7 @@ Bit32u BX_CPU_C::VMread32(unsigned encoding)
access_read_physical(pAddr, 4, (Bit8u*)(&field));
}
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 4, BX_READ, (Bit8u*)(&field));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 4, BX_VMCS_ACCESS | BX_READ, (Bit8u*)(&field));
return field;
}
@ -173,7 +173,7 @@ void BX_CPU_C::VMwrite32(unsigned encoding, Bit32u val_32)
access_write_physical(pAddr, 4, (Bit8u*)(&val_32));
}
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 4, BX_WRITE, (Bit8u*)(&val_32));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 4, BX_VMCS_ACCESS | BX_WRITE, (Bit8u*)(&val_32));
}
Bit64u BX_CPU_C::VMread64(unsigned encoding)
@ -195,7 +195,7 @@ Bit64u BX_CPU_C::VMread64(unsigned encoding)
access_read_physical(pAddr, 8, (Bit8u*)(&field));
}
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 8, BX_READ, (Bit8u*)(&field));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 8, BX_VMCS_ACCESS | BX_READ, (Bit8u*)(&field));
return field;
}
@ -219,7 +219,7 @@ void BX_CPU_C::VMwrite64(unsigned encoding, Bit64u val_64)
access_write_physical(pAddr, 8, (Bit8u*)(&val_64));
}
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 8, BX_WRITE, (Bit8u*)(&val_64));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 8, BX_VMCS_ACCESS | BX_WRITE, (Bit8u*)(&val_64));
}
////////////////////////////////////////////////////////////
@ -252,7 +252,7 @@ void BX_CPU_C::VMabort(VMX_vmabort_code error_code)
Bit32u abort = error_code;
bx_phy_address pAddr = BX_CPU_THIS_PTR vmcsptr + VMCS_VMX_ABORT_FIELD_ADDR;
access_write_physical(pAddr, 4, &abort);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 4, BX_WRITE, (Bit8u*)(&abort));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 4, BX_VMCS_ACCESS | BX_WRITE, (Bit8u*)(&abort));
shutdown();
}
@ -261,7 +261,7 @@ unsigned BX_CPU_C::VMXReadRevisionID(bx_phy_address pAddr)
Bit32u revision;
access_read_physical(pAddr + VMCS_REVISION_ID_FIELD_ADDR, 4, &revision);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr + VMCS_REVISION_ID_FIELD_ADDR, 4,
BX_READ, (Bit8u*)(&revision));
BX_VMCS_ACCESS | BX_READ, (Bit8u*)(&revision));
return revision;
}
@ -1682,9 +1682,9 @@ Bit32u BX_CPU_C::LoadMSRs(Bit32u msr_cnt, bx_phy_address pAddr)
for (Bit32u msr = 1; msr <= msr_cnt; msr++) {
access_read_physical(pAddr, 8, &msr_lo);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 8, BX_READ, (Bit8u*)(&msr_lo));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 8, BX_VMX_LOAD_MSR_ACCESS | BX_READ, (Bit8u*)(&msr_lo));
access_read_physical(pAddr + 8, 8, &msr_hi);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr + 8, 8, BX_READ, (Bit8u*)(&msr_hi));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr + 8, 8, BX_VMX_LOAD_MSR_ACCESS | BX_READ, (Bit8u*)(&msr_hi));
if (GET32H(msr_lo))
return msr;
@ -1716,7 +1716,7 @@ Bit32u BX_CPU_C::StoreMSRs(Bit32u msr_cnt, bx_phy_address pAddr)
for (Bit32u msr = 1; msr <= msr_cnt; msr++) {
access_read_physical(pAddr, 8, &msr_lo);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 8, BX_READ, (Bit8u*)(&msr_lo));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 8, BX_VMX_STORE_MSR_ACCESS | BX_READ, (Bit8u*)(&msr_lo));
if (GET32H(msr_lo))
return msr;
@ -1732,7 +1732,7 @@ Bit32u BX_CPU_C::StoreMSRs(Bit32u msr_cnt, bx_phy_address pAddr)
return msr;
access_write_physical(pAddr + 8, 8, &msr_hi);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr + 8, 8, BX_WRITE, (Bit8u*)(&msr_hi));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr + 8, 8, BX_VMX_STORE_MSR_ACCESS | BX_WRITE, (Bit8u*)(&msr_hi));
pAddr += 16; // to next MSR
}
@ -2275,7 +2275,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMCALL(bxInstruction_c *i)
Bit32u launch_state;
access_read_physical(BX_CPU_THIS_PTR vmcsptr + VMCS_LAUNCH_STATE_FIELD_ADDR, 4, &launch_state);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, BX_CPU_THIS_PTR vmcsptr + VMCS_LAUNCH_STATE_FIELD_ADDR, 4,
BX_READ, (Bit8u*)(&launch_state));
BX_VMCS_ACCESS | BX_READ, (Bit8u*)(&launch_state));
if (launch_state != VMCS_STATE_CLEAR) {
BX_ERROR(("VMFAIL: VMCALL with launched VMCS"));
@ -2351,7 +2351,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMLAUNCH(bxInstruction_c *i)
Bit32u launch_state;
access_read_physical(BX_CPU_THIS_PTR vmcsptr + VMCS_LAUNCH_STATE_FIELD_ADDR, 4, &launch_state);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, BX_CPU_THIS_PTR vmcsptr + VMCS_LAUNCH_STATE_FIELD_ADDR, 4,
BX_READ, (Bit8u*)(&launch_state));
BX_VMCS_ACCESS | BX_READ, (Bit8u*)(&launch_state));
if (vmlaunch) {
if (launch_state != VMCS_STATE_CLEAR) {
@ -2415,7 +2415,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMLAUNCH(bxInstruction_c *i)
launch_state = VMCS_STATE_LAUNCHED;
bx_phy_address pAddr = BX_CPU_THIS_PTR vmcsptr + VMCS_LAUNCH_STATE_FIELD_ADDR;
access_write_physical(pAddr, 4, &launch_state);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 4, BX_WRITE, (Bit8u*)(&launch_state));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 4, BX_VMCS_ACCESS | BX_WRITE, (Bit8u*)(&launch_state));
}
/*
@ -3235,7 +3235,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMCLEAR(bxInstruction_c *i)
Bit32u launch_state = VMCS_STATE_CLEAR;
access_write_physical(pAddr + VMCS_LAUNCH_STATE_FIELD_ADDR, 4, &launch_state);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr + VMCS_LAUNCH_STATE_FIELD_ADDR, 4,
BX_WRITE, (Bit8u*)(&launch_state));
BX_VMCS_ACCESS | BX_WRITE, (Bit8u*)(&launch_state));
if (pAddr == BX_CPU_THIS_PTR vmcsptr) {
BX_CPU_THIS_PTR vmcsptr = BX_INVALID_VMCSPTR;