Commit Graph

375 Commits

Author SHA1 Message Date
Stanislav Shwartsman
b08f208b9f Fixed compilation error 2002-12-24 20:59:55 +00:00
Stanislav Shwartsman
6acff47112 Implemented the following SSE instructions (sse_move.cc):
MOVSS_VssWss
MOVSS_WssVss
MOVSD_VsdWsd
MOVSD_WsdVsd
MOVMSKPS_GdVRps
MOVMSKPD_EdVRpd
MOVQ_VqWq
MOVQ_WqVq
SHUFPS_VpsWpsIb
SHUFPD_VpdWpdIb
2002-12-24 20:19:35 +00:00
Stanislav Shwartsman
4b59ecbc62 Implemented SSE/SSE2 duplicate opcodes in more intellegent way ... 2002-12-22 21:48:23 +00:00
Stanislav Shwartsman
29ab05b4da Removed duplicate SSE opcodes 2002-12-22 20:48:45 +00:00
Stanislav Shwartsman
e73df72525 implementation of additional SSE/SSE2 instructions 2002-12-22 20:42:56 +00:00
Stanislav Shwartsman
1cd38bb7dd Recommitted SSE code reorganization.
Fix in FXSAVE/FXRESTOR opcodes -> If the OSFXSR bitCR4 is not set, the FXRSTOR instruction does not restore the states of the XMM and MXCSR registers.
2002-12-22 20:13:00 +00:00
Bryce Denney
90d711e5d1 - add missing break stmts, pointed out by Shai Fultheim 2002-12-22 15:15:56 +00:00
Stanislav Shwartsman
f2f976d736 Add BX_INSTR_FETCH_DECODE_COMPLETED call even if an instruction hitten in ICache 2002-12-20 13:36:50 +00:00
Stanislav Shwartsman
4906ffef7c Clean Peter's commit with MOVNTDQ instruction implementation 2002-12-20 09:11:39 +00:00
Peter Tattam
c173034663 Patches to round off the x86-64 emulation to get the Linux x86-64 kernel and
sash to run.

1) fixed fetchdecode64.cc to fix the operand size at 64 bits in long mode for moves
   to/from CRx

2) minor patches to sse2.cc to fix unimplemented and 64 bit variants of sse2
instructions.
2002-12-20 07:11:29 +00:00
Bryce Denney
9b2914fd1d - Temporarily revert Stanislav's changes between 2002-12-18 and 2002-12-19.
Because source files were added/removed it would require an update
  of the windows and macos project files, so I want to wait until after 2.0.
    M Makefile.in         1.51 back to 1.50
    M cpu.h               1.121 back to 1.120
    M fetchdecode.cc      1.37 back to 1.36
    M fetchdecode64.cc    1.33 back to 1.32
    M sse.cc              1.17 back to 1.16
    A sse2.cc             1.27 back to 1.26  (added back)
    R sse_move.cc         removed
    R sse_pfp.cc          removed
- to bring these changes back again, all we have to do is
  "cvs update -j tmp-before1 -j tmp-after1"
2002-12-19 05:53:18 +00:00
Stanislav Shwartsman
aa361badf2 Reorganized SSE/SSE2 code
sse.cc -> general SSE stuff and SSE integer (MMX extensions)
sse_move.cc -> memory transfer and shuffle opcodes
sse_pfp.cc -> packed floating point operations
2002-12-18 22:33:44 +00:00
Bryce Denney
9a204569b7 - patch from Zwane on December 9. He writes:
> It's safe to deliver ExtINT as Fixed in our setup and just leave a comment
  > there instead of the panic.
2002-12-14 08:48:20 +00:00
Christophe Bothamy
16ebfdb9e1 - update for macos compile 2002-12-12 15:29:45 +00:00
Christophe Bothamy
ff89875ffd - remove unused (seems to be) typedef 2002-12-12 13:26:29 +00:00
Stanislav Shwartsman
04c7d9301b implemented
PINSRW_VdqEdIb
PEXTRW_VdqEdIb
PINSRW_PqEdIb
PEXTRW_PqEdIb

instructions
2002-12-02 21:24:09 +00:00
Stanislav Shwartsman
3012e7c361 Fixed representation and aligment of FPU/MMX register(s).
Description/justification:

Endian  Host byte order         Guest (x86) byte order
======================================================
Little  FFFFFFFFEEAAAAAA        FFFFFFFFEEAAAAAA
Big     AAAAAAEEFFFFFFFF	FFFFFFFFEEAAAAAA

F - fraction/mmx
E - exponent
A - aligment
2002-11-30 17:15:59 +00:00
Stanislav Shwartsman
57fd94744d Implemented MOVQ2DQ/MOVDQ2Q instructions
Small fixes with MMX environment
2002-11-30 14:42:41 +00:00
Stanislav Shwartsman
bcd57bdcaf *** Current duplicate SSE/SSE2 instructions list ***
MOVUPS_VpsWps  (0f 10) = MOVUPD_VpdWpd  (66 0f 10) = MOVDQU_VdqWdq (f3 0f 6f)
MOVUPS_WpsVps  (0f 11) = MOVUPD_WpdVpd  (66 0f 11) = MOVDQU_WdqVdq (f3 0f 7f)
MOVAPS_VpsWps  (0f 28) = MOVAPD_VpdWpd  (66 0f 28) = MOVDQA_VdqWdq (66 0f 6f)
MOVAPS_WpsVps  (0f 29) = MOVAPD_WpdVpd  (66 0f 29) = MOVDQA_WdqVdq (66 0f 7f)

MOVNTPS_MdqVps (0f 2b) = MOVNTPD_MdqVpd (66 0f 2b)
MOVLPS_VpsMq   (0f 12) = MOVLPD_VsdMq   (66 0f 12)
MOVLPS_MqVps   (0f 13) = MOVLPD_MqVsd   (66 0f 13)
MOVHPS_VpsMq   (0f 16) = MOVHPD_VpdMq   (66 0f 16)
MOVHPS_MqVps   (0f 17) = MOVHPD_MqVpd   (66 0f 17)

ANDPS_VpsWps   (0f 54) = ANDPD_VpdWpd   (66 0f 54) = PAND_VpdWpd   (66 0f db)
ANDNPS_VpsWps  (0f 55) = ANDNPD_VpdWpd  (66 0f 55) = PANDN_VpdWpd  (66 0f df)
ORPS_VpsWps    (0f 56) = ORPD_VpdWpd    (66 0f 56) = POR_VpdWpd    (66 0f eb)
XORPS_VpsWps   (0f 57) = XORPD_VpdWpd   (66 0f 57) = PXOR_VpdWpd   (66 0f ef)

Removed dupes
2002-11-25 21:58:55 +00:00
Bryce Denney
3edf45a1d9 - regenerate makefile dependencies 2002-11-25 15:05:51 +00:00
Stanislav Shwartsman
a4806d3fce Fixed the MXCSR mask value 2002-11-22 21:42:46 +00:00
Stanislav Shwartsman
9bf3b44665 Fixed a little logic problem with FPU TWD save/restore 2002-11-22 21:33:12 +00:00
Stanislav Shwartsman
2b2e773dde Fixed a problem in LDMXCSR instruction
Beta version of FXSAVE/FXRSTOR instructions implementation
(still imcomplete, doesn't fully restore FPU state)
2002-11-22 21:21:31 +00:00
Stanislav Shwartsman
b4f060e698 Initialize SSE environment at reset 2002-11-22 09:36:28 +00:00
Bryce Denney
dcedff8d46 - fix some minor compile bugs that appear when you mix up instrumentation,
debugger, SMP, and x86-64.  A few macros were missing the CPU_ID argument,
  and a few passed nonexistent variables to the instrumentation macros.
- I changed CPU_ID into a plain old macro instead of an inline call to a
  trivial which_cpu() function, and removed which_cpu().

Modified Files:
  cpu/cpu.h cpu/ctrl_xfer64.cc debug/dbg_main.cc
2002-11-21 18:22:03 +00:00
Christophe Bothamy
3104ba6bea - fix [ 625878 ] reset doesn't reset something(?)
In bx_cpu_c::reset method I set bx_cpu->async_event to 2
  so execution in the cpu_loop gets stopped early.

  Previously, async_event was set to 0, and with repeatable
  instructions, after reset, eip was incremented by the instruction
  length, so execution would resume at 0xffffX (X being >0, the current
  instruction length).

  In halt state I check now for reset with async_event is 2, so
  reset works also when the cpu is halted. (update to Peter change)

  I hope I fixed this the right way, please report any strange behaviour.
2002-11-21 08:08:29 +00:00
Bryce Denney
9b14101a05 - rewrite typecast of temp to Bit64u to keep VC++ happy. I don't really
know what it thought was wrong.
2002-11-19 05:53:47 +00:00
Bryce Denney
dcc6d6038a - we forgot to initialize trace_reg and kill_bochs_request to 0. 2002-11-19 05:52:52 +00:00
Bryce Denney
97f911d1fe - when VC++ sees local variables in a for statement, it doesn't think
that they go out of scope at the end, so it complains about duplicate
  definitions.
2002-11-19 05:51:52 +00:00
Bryce Denney
0a7cb3a43c - apply patch.ifdef-disabled-options. Comments from that patch are below:
For a whole lot of configure options, I put #if...#endif around code that
  is specific to the option, even in files which are normally only compiled
  when the option is on.  This allows me to create a MS Visual C++ 6.0
  workspace that supports many of these options.  The workspace will basically
  compile every file all the time, but the code for disabled options will
  be commented out by the #if...#endif.

  This may one day lead to simplification of the Makefiles and configure
  scripts, but for the moment I'm leaving Makefiles and configure scripts
  alone.

  Affected options:
    BX_SUPPORT_APIC (cpu/apic.cc)
    BX_SUPPORT_X86_64 (cpu/*64.cc)
    BX_DEBUGGER (debug/*)
    BX_DISASM (disasm/*)
    BX_WITH_nameofgui (gui/*)
    BX_SUPPORT_CDROM (iodev/cdrom.cc)
    BX_NE2K_SUPPORT (iodev/eth*.cc, iodev/ne2k.cc)
    BX_SUPPORT_APIC (iodev/ioapic.cc)
    BX_IODEBUG_SUPPORT (iodev/iodebug.cc)
    BX_PCI_SUPPORT (iodev/pci*.cc)
    BX_SUPPORT_SB16 (iodev/sb*.cc)

Modified Files:
  cpu/apic.cc cpu/arith64.cc cpu/ctrl_xfer64.cc
  cpu/data_xfer64.cc cpu/fetchdecode64.cc cpu/logical64.cc
  cpu/mult64.cc cpu/resolve64.cc cpu/shift64.cc cpu/stack64.cc
  debug/Makefile.in debug/crc.cc debug/dbg_main.cc debug/lexer.l
  debug/linux.cc debug/parser.c debug/parser.y
  disasm/dis_decode.cc disasm/dis_groups.cc gui/amigaos.cc
  gui/beos.cc gui/carbon.cc gui/macintosh.cc gui/rfb.cc
  gui/sdl.cc gui/term.cc gui/win32.cc gui/wx.cc gui/wxdialog.cc
  gui/wxmain.cc gui/x.cc iodev/cdrom.cc iodev/eth.cc
  iodev/eth_arpback.cc iodev/eth_fbsd.cc iodev/eth_linux.cc
  iodev/eth_null.cc iodev/eth_packetmaker.cc iodev/eth_tap.cc
  iodev/eth_tuntap.cc iodev/eth_win32.cc iodev/ioapic.cc
  iodev/iodebug.cc iodev/ne2k.cc iodev/pci.cc iodev/pci2isa.cc
  iodev/sb16.cc iodev/soundlnx.cc iodev/soundwin.cc
2002-11-19 05:47:45 +00:00
Bryce Denney
add9107dae - add BOCHSAPI to bxICache_c 2002-11-15 18:12:04 +00:00
Stanislav Shwartsman
3217759a75 Implemented
PSHUFLW_VqWqIb, PSHUFHW_VqWqIb instructions
2002-11-15 17:34:47 +00:00
Stanislav Shwartsman
da8a2a71b1 Fixed bug PSHUFW instruction 2002-11-15 17:02:06 +00:00
Stanislav Shwartsman
62e362afc2 just typo 2002-11-15 15:55:36 +00:00
Stanislav Shwartsman
34dd74fe6c Fixed BUG in PMADDWD instruction 2002-11-15 15:51:12 +00:00
Stanislav Shwartsman
189f64b533 SSE2 shifts uses as count only low 64 bits of XMM register/mem128 2002-11-15 14:48:24 +00:00
Stanislav Shwartsman
d4426dc60b More bugfix in SSE 2002-11-15 14:33:44 +00:00
Stanislav Shwartsman
88ce9917e6 Replace BX_PANIC to BX_INFO for FXSAVE/FXRSTOR instruction
because their is required for booting Windows with SSE enabled.
2002-11-15 13:10:06 +00:00
Stanislav Shwartsman
121de7d960 Fixed bug with decoding of Group15 2002-11-15 13:05:19 +00:00
Stanislav Shwartsman
ccbc8e0ef7 MOVAPS/MOVAPD have a different exceptions 2002-11-15 12:44:39 +00:00
Stanislav Shwartsman
65b8712d04 More tuning of SSE 2002-11-14 19:59:29 +00:00
Stanislav Shwartsman
7ccf1de78f According to the Intel (and AMD) manuals a lot different SSE/SSE2 opcodes has EXACTLY the same operation.
Deleted first three redundant opcodes (move integer data):
   MOVLPS_VpsMq   (0f 12) = MOVLPD_VsdMq   (66 0f 12)
   MOVLPS_MqVps   (0f 13) = MOVLPD_MqVsd   (66 0f 13)
   MOVHPS_VpsMq   (0f 16) = MOVHPD_VpdMq   (66 0f 16)
   MOVHPS_MqVps   (0f 17) = MOVHPD_MqVpd   (66 0f 17)

Until under examination:
XORPS,XORPD
ORPS,ORPD
ANDPS,ANDPD
ANDNPS,ANDNPD
MOVUPS,MOVUPD
2002-11-13 22:24:03 +00:00
Stanislav Shwartsman
968b2744f4 According to the Intel (and AMD) manuals a lot different SSE/SSE2 opcodes
has EXACTLY the same operation.

Deleted first three redundant opcodes:
   MOVAPS_VpsWps  (0f 28) = MOVAPD_VpdWpd  (66 0f 28)
   MOVAPS_WpsVps  (0f 29) = MOVAPD_WpdVpd  (66 0f 29)
   MOVNTPS_MdqVps (0f 2b) = MOVNTPD_MdqVpd (66 0f 2b)

Until checking:
XORPS,XORPD
ORPS,ORPD
ANDPS,ANDPD
ANDNPS,ANDNPD
MOVUPS,MOVUPD
MOVLPS,MOVLPD
MOVHPS,MOVHPD
2002-11-13 21:35:17 +00:00
Stanislav Shwartsman
5803e20240 Changed policy of SSE/SSE2 checking 2002-11-13 21:00:05 +00:00
Stanislav Shwartsman
6c6519a73d Implemented SSE2 integer instructions:
PMULHW_VdqWdq
PMULHUW_VdqWdq
PMULLW_VdqWdq
MOVNTI_MdGd

Somedoby that is the difference between MOVNTPD, MOVNTPS, MPVNTDQ instructions ?
2002-11-09 19:22:00 +00:00
Stanislav Shwartsman
bc0463f08a Implemented
PSRLDQ_WdqIb
PSLLDQ_WdqIb
instructions
2002-11-08 21:09:17 +00:00
Stanislav Shwartsman
790430bf22 #UD exception condition for SSE instructions fixed 2002-11-08 20:27:42 +00:00
Stanislav Shwartsman
3cd6f7282d Alloc setting OFXCSR (bit9) of CR4 in SSE/SSE2 enabled 2002-11-08 20:26:12 +00:00
Stanislav Shwartsman
a814c00278 MOVD_EdVd: bugfix 2002-11-08 17:50:20 +00:00
Stanislav Shwartsman
0df9c9af85 Implemented integer SSE2 instructions:
PSRLW_PdqIb
PSRLD_PdqIb
PSRLQ_PdqIb
PSLLW_PdqIb
PSLLD_PdqIb
PSLLQ_PdqIb
PSRAW_PdqIb
PSRAD_PdqIb
PSRLW_VdqWdq
PSRLD_VdqWdq
PSRLQ_VdqWdq
PSRAW_PdqWdq
PSRAD_PdqWdq
PSLLW_VdqWdq
PSLLD_VdqWdq
PSLLQ_VdqWdq
PMOVMSKB_GdVRdq
PMULUDQ_VdqWdq
PMINUB_VdqWdq
PMINSW_VdqWdq
PMAXUB_VdqWdq
PMAXSW_VdqWdq

Fixed bug in the PMINUB_PqQq and PMAXUB_PqQq SSE instructions
2002-11-08 17:47:46 +00:00