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88 Commits

Author SHA1 Message Date
Stanislav Shwartsman
92568f7525 Faster 32-bit emulation wwith 64-bit enabled mode. 
~10% speedup byu optimization of 32-bit mem access
 2008-06-12 19:14:40 +00:00
Stanislav Shwartsman
ff332232d4 Fixed compiler warning 2008-05-26 21:51:46 +00:00
Stanislav Shwartsman
d295371450 - Correctly handle segment a byte in BIG real mode 2008-05-26 21:46:39 +00:00
Stanislav Shwartsman
77fbc2c187 Fixed LAR/LSL in 64-bit mode, compilation error fixes 2008-05-25 15:53:29 +00:00
Stanislav Shwartsman
ec1ff39a5f Splitted memory access methods for 32 and 64-bit code. 
The 64-bit code got >10% speedup, the 32-bit code also got about 2% because laddr cacluation optimization
 2008-05-10 18:10:53 +00:00
Stanislav Shwartsman
64a80c8a2d - Added canonical check for SYSENTER MSRs in WRMSR 
- Fixed LLDT and LTR instructions in 64-bit mode
- Fixed error code for not 64-bit CS in interrupt from long mode
 2008-05-04 21:25:16 +00:00
Stanislav Shwartsman
ea48400435 Chnage back write variables order 2008-04-24 22:41:46 +00:00
Stanislav Shwartsman
b504253645 Added canonical check for LIDT/LGDT instructions in 64-bit mode 2008-04-24 19:34:01 +00:00
Stanislav Shwartsman
3c7949948b - Added >32bit physical address PANIC in PSE mode with 4M paging 
- Fixed LAR/LSL instructions in 64-bit mode
 2008-04-22 22:05:38 +00:00
Stanislav Shwartsman
36926542e6 Fixed canonical fault exceptions for call_far, interrupt, lldt and ltr instructions 2008-04-16 22:08:46 +00:00
Stanislav Shwartsman
892fa99c6f - prefetch hint should be NOP when use in register mode 
- #GP when trying to set reserved bits of CR4_HI in 64-bit mode
- #GP when trying to set reserved bits of EFER MSR
- clear upper part of RSI/RDI when executing rep instructions with 32-bit asize
  even if no repeat iterations were executed (because of RCX=0 for example)
- write SYSENTER_EIP_MSR and SYSENTER_ESP_MSR as 64-bit when x86_64 supported
- set MSR_FMASK reset value
- MSR_FMASK should be 32-bit only
- check for fetch permissions when doing ITLB lookup
- #GP when trying to write non-canonical address to MSR_CSTAR or MSR_LSTAR
- correct repeat instructions timing
- mark TSS busy in TR after it is loaded
 2008-04-16 16:44:06 +00:00
Stanislav Shwartsman
f3a91710e4 Split access_linear to access_read_linear and access_write_linear 2008-03-29 18:18:08 +00:00
Stanislav Shwartsman
167c7075fb Use fastcall gcc attribute for all cpu execution functions - this pure "compiler helper" optimization brings additional 2% speedup to Bochs code 2008-03-22 21:29:41 +00:00
Stanislav Shwartsman
457152334e step2 in XSAVE implementation 2008-02-13 16:45:21 +00:00
Stanislav Shwartsman
a2897933a3 white space cleanup 2008-02-02 21:46:54 +00:00
Stanislav Shwartsman
9f4dd0df8a Fixed BX_ERROR message in LTR instruction 2008-01-29 06:23:49 +00:00
Stanislav Shwartsman
932d758547 Do not try to update access/dirty bit if it was already set 2008-01-20 17:46:02 +00:00
Stanislav Shwartsman
d9984bb3a1 Eliminate BxResolve call from the heart of cpu loop and move into instructions that really require this calculation. Yes, it blows the code of EVERY CPU method but it has >15% speedup ! 2008-01-10 19:37:56 +00:00
Stanislav Shwartsman
838fb2a048 Fixing V2008 warnings - they found a bug in sse_pfp.cc ! 2007-12-23 17:21:28 +00:00
Stanislav Shwartsman
d830c301cf Fixed 64-bit versions of LOOP instructions, some cleanups 2007-12-21 17:30:49 +00:00
Stanislav Shwartsman
5d4e32b8da Avoid pointer params for every read_virtual_* except 16-byte SSE and 10-byte x87 reads 2007-12-20 20:58:38 +00:00
Stanislav Shwartsman
b516589e4e Changes in write_virtual_* and pop_* functions -> avoid moving parameteres by pointer 2007-12-20 18:29:42 +00:00
Stanislav Shwartsman
af9a14ff3b cleanups 2007-11-22 21:52:55 +00:00
Stanislav Shwartsman
cdc9a09090 Split more opcodes 2007-11-18 18:24:46 +00:00
Stanislav Shwartsman
83f6eb6945 Changes copyrights for the files I wrote :) 
Also split EqId G1 group for x86-64
 2007-11-17 23:28:33 +00:00
Stanislav Shwartsman
42fdd8a3a1 During Bochs benchmarking I figured out that hostasm actually slow down the emulation ... so remove this ugly code which also doesn't help :) 
speedup flags update for some instructions - idea was taken from DT patch by h.johansson
 2007-10-21 22:07:33 +00:00
Stanislav Shwartsman
26848ad07d Change ARPL error message to BX_DEBUG (happens too offen in win98) 2007-10-12 19:45:12 +00:00
Stanislav Shwartsman
dbb91069f4 Added SSE4_2 instructions emulation 2007-10-01 19:59:37 +00:00
Stanislav Shwartsman
a0d0de9fd4 Fixed ARPL issue mentioned in 
Attacks on Virtual Machine Emulators
document by Symantec
 2007-09-30 18:47:41 +00:00
Stanislav Shwartsman
e812f81e7b Fixes in zero upper ECX 2007-09-25 16:11:32 +00:00
Stanislav Shwartsman
c184a3a2ba Removed redundant mem-only checks - handled in fetchdecode now 2007-03-23 14:50:45 +00:00
Stanislav Shwartsman
b8787fd5a7 Some code cleanups and warning fixes 2007-03-14 21:15:15 +00:00
Stanislav Shwartsman
c24627c00f Implemented CLFLUSH instruction 
Set of minor fixes for correctness
 2007-01-28 21:27:31 +00:00
Stanislav Shwartsman
8221fa6838 - Fixed zero upper 32-bit part of GPR in x86-64 mode 
- CMOV_GdEd should zero upper 32-bit part of GPR register even if the
    'cmov' condition was false !
 2007-01-26 22:12:05 +00:00
Stanislav Shwartsman
f8003098b1 Rename SSE4 to SSE3E to match intel docs. SSE4 coming later ;) 
Fixed "last prefix" for REX in 64-bit mode
 2007-01-25 19:09:41 +00:00
Stanislav Shwartsman
0e991964fd incorrectly committed debug code 2007-01-13 10:45:32 +00:00
Stanislav Shwartsman
dd00bc66d0 Fixed disasm in 64bit mode, added new accessor for printing 64bit values 2007-01-13 10:43:31 +00:00
Stanislav Shwartsman
9db896d100 minor x86_64 fixes and cleanups 2007-01-12 22:47:21 +00:00
Stanislav Shwartsman
fdac9efa9b Fixed ton of code duplication. 
Do not save/restore XMM8-XMM15 not in 64-bit mode
 2006-08-31 18:18:17 +00:00
Stanislav Shwartsman
54fb3b769a Fixed LDT 16-bit limit, must support all 32-bit values. 2006-08-22 19:06:03 +00:00
Stanislav Shwartsman
49d7b4614f Fixed another bug generator - duplication between descriptor type field and four descriptor cache bits 2006-06-12 16:58:27 +00:00
Stanislav Shwartsman
8b55085c76 Merge tss286 and tss386 segment descriptor cache fields to one structure 2006-05-21 20:41:48 +00:00
Stanislav Shwartsman
5c3fba4399 Support access to SMRAM in memory object 
Cleanup in CPU code
 2006-03-26 18:58:01 +00:00
Stanislav Shwartsman
7b6c2587a9 Now devices could be compiled separatelly from CPU 
Averything that required cpu.h include now has it explicitly and there are a lot of files not dependant by CPU at all which will compile a lot faster now ...
 2006-03-06 22:03:16 +00:00
Stanislav Shwartsman
bf855506a3 Change set_FLAGS(0) by clear_FLAG () 
set_FLAGS(1) by assert_FLAG()
 2005-10-15 21:01:36 +00:00
Volker Ruppert
fa68f44d94 - compilation error fixed 2005-10-02 15:26:51 +00:00
Stanislav Shwartsman
7869ab425f LTR should #GP when loading NULL selector 
fixed check for SYSENTER/SYSEXIT instructions
according to new Intel references
 2005-10-01 07:47:00 +00:00
Stanislav Shwartsman
b28ed3be69 Fix LDT.limit < 7 check 
Indent for protect_ctrl.cc code
 2005-08-21 18:23:36 +00:00
Stanislav Shwartsman
169fa0c574 Clearify the code. x86-64 code always running in pmode so it is not needed to check if we are in protected mode everytime 2005-07-10 20:32:32 +00:00
Stanislav Shwartsman
a9dd851fd6 Fixed several PANIC cases: 
the PANIC message TSS.limit < 103 should never appear anymore
 2005-06-22 18:13:45 +00:00