mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Removed redundant mem-only checks - handled in fetchdecode now

Browse Source
This commit is contained in:
Stanislav Shwartsman 2007-03-23 14:50:45 +00:00
parent ef542b3790
commit c184a3a2ba
2 changed files with 2 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
bochs/cpu/paging.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: paging.cc,v 1.81 2007-01-13 10:43:31 sshwarts Exp $
// $Id: paging.cc,v 1.82 2007-03-23 14:50:45 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -552,11 +552,6 @@ void BX_CPU_C::INVLPG(bxInstruction_c* i)
#if BX_CPU_LEVEL >= 4
invalidate_prefetch_q();
if (i->modC0()) {
BX_INFO(("INVLPG: op is a register"));
UndefinedOpcode(i);
}
if (!real_mode() && CPL!=0) {
BX_ERROR(("INVLPG: priveledge check failed, generate #GP(0)"));
exception(BX_GP_EXCEPTION, 0, 0);

44
bochs/cpu/protect_ctrl.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: protect_ctrl.cc,v 1.57 2007-03-14 21:15:15 sshwarts Exp $
// $Id: protect_ctrl.cc,v 1.58 2007-03-23 14:50:45 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -631,12 +631,6 @@ void BX_CPU_C::VERW_Ew(bxInstruction_c *i)
void BX_CPU_C::SGDT_Ms(bxInstruction_c *i)
{
/* op1 is a register or memory reference */
if (i->modC0()) {
BX_ERROR(("SGDT_Ms: use of register is undefined opcode"));
UndefinedOpcode(i);
}
Bit16u limit_16 = BX_CPU_THIS_PTR gdtr.limit;
Bit32u base_32 = BX_CPU_THIS_PTR gdtr.base;
@ -646,12 +640,6 @@ void BX_CPU_C::SGDT_Ms(bxInstruction_c *i)
void BX_CPU_C::SIDT_Ms(bxInstruction_c *i)
{
/* op1 is a register or memory reference */
if (i->modC0()) {
BX_ERROR(("SIDT_Ms: use of register is undefined opcode"));
UndefinedOpcode(i);
}
Bit16u limit_16 = BX_CPU_THIS_PTR idtr.limit;
Bit32u base_32 = BX_CPU_THIS_PTR idtr.base;
@ -661,12 +649,6 @@ void BX_CPU_C::SIDT_Ms(bxInstruction_c *i)
void BX_CPU_C::LGDT_Ms(bxInstruction_c *i)
{
/* operand might be a register or memory reference */
if (i->modC0()) {
BX_ERROR(("LGDT: must be memory reference"));
UndefinedOpcode(i);
}
if (v8086_mode()) {
BX_ERROR(("LGDT: not recognized in virtual-8086 mode"));
exception(BX_GP_EXCEPTION, 0, 0);
@ -708,12 +690,6 @@ void BX_CPU_C::LGDT_Ms(bxInstruction_c *i)
void BX_CPU_C::LIDT_Ms(bxInstruction_c *i)
{
/* operand might be a register or memory reference */
if (i->modC0()) {
BX_ERROR(("LIDT: must be memory reference"));
UndefinedOpcode(i);
}
if (v8086_mode()) {
BX_ERROR(("LIDT: not recognized in virtual-8086 mode"));
exception(BX_GP_EXCEPTION, 0, 0);
@ -752,12 +728,6 @@ void BX_CPU_C::LIDT_Ms(bxInstruction_c *i)
void BX_CPU_C::SGDT64_Ms(bxInstruction_c *i)
{
/* op1 is a register or memory reference */
if (i->modC0()) {
BX_ERROR(("SGDT64_Ms: use of register is undefined opcode"));
UndefinedOpcode(i);
}
Bit16u limit_16 = BX_CPU_THIS_PTR gdtr.limit;
Bit64u base_64 = BX_CPU_THIS_PTR gdtr.base;
@ -767,12 +737,6 @@ void BX_CPU_C::SGDT64_Ms(bxInstruction_c *i)
void BX_CPU_C::SIDT64_Ms(bxInstruction_c *i)
{
/* op1 is a register or memory reference */
if (i->modC0()) {
BX_ERROR(("SIDT64_Ms: use of register is undefined opcode"));
UndefinedOpcode(i);
}
Bit16u limit_16 = BX_CPU_THIS_PTR idtr.limit;
Bit64u base_64 = BX_CPU_THIS_PTR idtr.base;
@ -811,12 +775,6 @@ void BX_CPU_C::LIDT64_Ms(bxInstruction_c *i)
{
BX_ASSERT(protected_mode());
/* operand might be a register or memory reference */
if (i->modC0()) {
BX_ERROR(("LIDT64_Ms: must be memory reference"));
UndefinedOpcode(i);
}
if (CPL != 0) {
BX_ERROR(("LIDT64_Ms: CPL != 0 in long mode"));
exception(BX_GP_EXCEPTION, 0, 0);