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1111 Commits

Author SHA1 Message Date
Stanislav Shwartsman
7e629dedad remove dbg print 2007-09-26 19:10:41 +00:00
Stanislav Shwartsman
44a04a5fa3 readability/writeability bit should not be checked in 64-bit mode 2007-09-26 19:09:10 +00:00
Stanislav Shwartsman
dcb0335ae9 Debug first instruction in exception handler after exception 2007-09-26 18:07:39 +00:00
Stanislav Shwartsman
e812f81e7b Fixes in zero upper ECX 2007-09-25 16:11:32 +00:00
Stanislav Shwartsman
3e3254ecc4 some speedup for SSE code - achived by code simplification 2007-09-20 22:55:03 +00:00
Stanislav Shwartsman
91e6ca8d5c Implemented MTRR support 
Fixes in #PF exception priority
 2007-09-20 17:33:35 +00:00
Stanislav Shwartsman
0dc4badfbb Added SSE4A and SSE4_2 to disassembler 
Implemented POPCNT instruction
 2007-09-19 19:38:10 +00:00
Stanislav Shwartsman
70f513b07b Make efer control MSR separate register 2007-09-10 20:47:08 +00:00
Stanislav Shwartsman
b4df87c9b0 Added CVS id 2007-09-10 16:04:41 +00:00
Stanislav Shwartsman
412eeeeb7c Get crregs definition to separate file from cpu.h 2007-09-10 16:00:15 +00:00
Stanislav Shwartsman
016660698e just code cleanup, preparation for future 2007-08-31 18:09:34 +00:00
Stanislav Shwartsman
5ac1bb6646 rewrite page fault 2007-08-30 16:48:10 +00:00
Stanislav Shwartsman
b64fc08c54 implement prefetch hint opcodes 2007-08-23 16:47:51 +00:00
Stanislav Shwartsman
4555cc9be3 ud2b opcode should have modrm byte 2007-08-18 13:51:16 +00:00
Stanislav Shwartsman
895891b673 Implemented #AC check under configure option 
Fixes in misaligned SSE support
 2007-07-31 20:25:52 +00:00
Stanislav Shwartsman
58a2595bca Misaligned SSE support 2007-07-15 19:03:39 +00:00
Stanislav Shwartsman
38d1f39c77 Converted CR0 bits to one register similar to CR4 - a bit slower but helps with other features implemntation 2007-07-09 15:16:14 +00:00
Stanislav Shwartsman
7c6c2bb520 Removed PANIC message 2007-06-08 09:25:30 +00:00
Stanislav Shwartsman
65a99eb736 Change BX_ERROR to BX_DEBUG 2007-04-25 20:14:15 +00:00
Stanislav Shwartsman
55365ba713 Minimize usage of result register 2007-04-19 19:09:52 +00:00
Stanislav Shwartsman
1c3e703394 Fixed DAZ handling by CVT instructions 2007-04-19 18:50:57 +00:00
Stanislav Shwartsman
5189cfbf10 SSE4 support 2007-04-19 16:12:21 +00:00
Stanislav Shwartsman
f6af99dead Some variables renaming + CPU vendor variable defition 2007-04-17 21:38:51 +00:00
Stanislav Shwartsman
6c139a9c8c Define LIN and PHY address size in config.h 2007-04-14 10:05:30 +00:00
Stanislav Shwartsman
3886e35bcb Clean code duplication 2007-04-09 21:55:07 +00:00
Stanislav Shwartsman
223b9fda0e Fixed RIP relative mode when in 32-bit address size 2007-04-09 21:15:00 +00:00
Stanislav Shwartsman
e26609fa97 Support for Intel LSS/LFS/LGS in 64-bit mode 
TODO: have both AMD and Intelk versions
 2007-04-09 20:28:15 +00:00
Stanislav Shwartsman
b6c8275cfd remove old PIT model and always use Greg Alexander's new one 2007-04-08 21:57:06 +00:00
Volker Ruppert
f8aec91820 - fixed some MSVC warnings 2007-04-06 15:22:17 +00:00
Stanislav Shwartsman
65b9b46de3 Fix for legacy compilers 2007-04-04 16:55:50 +00:00
Stanislav Shwartsman
bdc4905c8a Correctly detect SSE2 and SSE instructions and #UD when SSE2 is OFF for SSE 2007-04-02 10:46:33 +00:00
Stanislav Shwartsman
4bb19c2dc3 Fixed deciding and disasm of CALL in 64-bit mode (no 16-bit calls allowed) 2007-03-28 21:20:09 +00:00
Stanislav Shwartsman
26f08fdb2c Change my e-mail to #SF one 2007-03-23 21:27:13 +00:00
Stanislav Shwartsman
c184a3a2ba Removed redundant mem-only checks - handled in fetchdecode now 2007-03-23 14:50:45 +00:00
Stanislav Shwartsman
ef542b3790 Learn to decode and disassemble VMX opcodes 
No fetchdecode support but everything is ready
 2007-03-23 14:35:50 +00:00
Stanislav Shwartsman
1ec33ec518 Correctly #UD on aliased instructions when no SSE2 is configured 2007-03-22 22:51:41 +00:00
Stanislav Shwartsman
0436125d60 Some cleanup in lazy flags CF handling 2007-03-18 19:29:17 +00:00
Stanislav Shwartsman
b8787fd5a7 Some code cleanups and warning fixes 2007-03-14 21:15:15 +00:00
Stanislav Shwartsman
8ce336cad3 Fixed PANIC message 2007-03-10 09:04:39 +00:00
Stanislav Shwartsman
05ea111e1c Clean CPU debug methods in main cpu_loop 2007-03-06 17:47:18 +00:00
Stanislav Shwartsman
8067503c67 PUSHA/POP instructions rewritten, fixed PANIC message 2007-03-02 21:03:25 +00:00
Stanislav Shwartsman
d3252fbc1c Removed unneeded invalidate_prefetch_q from RDMSR instruction 2007-02-23 22:08:43 +00:00
Stanislav Shwartsman
8d2060b855 Replace access_linear by read_virtual_xword when applicable 2007-02-03 21:36:40 +00:00
Stanislav Shwartsman
2f9e1bee68 fixed code duplication and comments 2007-02-03 17:56:35 +00:00
Stanislav Shwartsman
372ac39050 Report some cache info in CPUID - port from QEMU 2007-01-29 17:56:03 +00:00
Stanislav Shwartsman
c24627c00f Implemented CLFLUSH instruction 
Set of minor fixes for correctness
 2007-01-28 21:27:31 +00:00
Stanislav Shwartsman
82607c4a35 Safety net - comment BX_WRITE_32BIT_REG macro - always use WRITE_32BIT_REGZ instead ! 2007-01-26 22:16:59 +00:00
Stanislav Shwartsman
8221fa6838 - Fixed zero upper 32-bit part of GPR in x86-64 mode 
- CMOV_GdEd should zero upper 32-bit part of GPR register even if the
    'cmov' condition was false !
 2007-01-26 22:12:05 +00:00
Stanislav Shwartsman
acd1a05f6f Fixed bugs for SSE3E execution and decoding 2007-01-25 21:44:35 +00:00
Stanislav Shwartsman
f8003098b1 Rename SSE4 to SSE3E to match intel docs. SSE4 coming later ;) 
Fixed "last prefix" for REX in 64-bit mode
 2007-01-25 19:09:41 +00:00