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1092 Commits

Author SHA1 Message Date
Stanislav Shwartsman
4b66fecaad split Bochs CPU TLB to DTLB and ITLB to avoid aliasing conflicts between them. ~5% speedup measured 2019-12-09 18:37:02 +00:00
Stanislav Shwartsman
8befc3bf82 make separate class for TLB to be used in CPU class. preparation to DTLB and ITLB split of TLB structure 2019-12-09 16:49:51 +00:00
Stanislav Shwartsman
44b3ebeca2 remove BX_TRUE/BX_FALSE macros, use stdc++ true/false instead 2019-12-09 16:44:36 +00:00
Stanislav Shwartsman
12d228abde split vmx initialization to multiple methods for better code readability, improve VMX error messages 2019-12-08 20:46:51 +00:00
Stanislav Shwartsman
06d826755b increase max configurable msrs to 0x1000 again 2019-12-06 12:31:51 +00:00
Stanislav Shwartsman
0c75e0beaf extract xcr0_support bits calculation to a function 2019-12-06 09:23:28 +00:00
Stanislav Shwartsman
4e9e3f85de simplify code by merging two opcodes with similar behavior 2019-11-27 15:31:32 +00:00
Stanislav Shwartsman
d766cc8112 implemented SCA (Side-Channel-Attack) Prevention reporting and corresponding MSR registers, enabled for Icelake-U CPU definition 2019-10-26 20:09:30 +00:00
Stanislav Shwartsman
bb5ccc97c1 remove unused function parameter 2019-10-16 19:53:04 +00:00
Stanislav Shwartsman
9c61e9e9f5 remove unused function parameter 2019-10-16 19:48:21 +00:00
Stanislav Shwartsman
10c23b5d39 implement fasstring for 64-bit mode as well 2019-10-14 19:50:47 +00:00
Stanislav Shwartsman
ee3f1b91a3 allow fast string only for forward strings and simplify the code 2019-10-14 14:45:01 +00:00
Stanislav Shwartsman
f0245b5f2b introduce special handlers for zero-idiom instructions - ~1% speedup to simulation. infra for fast string emulation in 64-bit mode 2019-10-14 06:40:19 +00:00
Stanislav Shwartsman
2ae332cce8 patch by Luigu.B - significantly speedup multi-threaded guest simulation 2019-08-09 19:57:13 +00:00
Stanislav Shwartsman
4d10852c04 impemented recently published VP2INTERSECTD/Q instructions 2019-05-25 19:07:09 +00:00
Stanislav Shwartsman
f8ec18acd5 fix decode/disasm of AVX512-VBMI2 VPSH*D* opcodes 2019-01-27 18:52:03 +00:00
Stanislav Shwartsman
965bcc2606 support 64-bit in 'info tab' debugger command and also speed it up significantly 2018-08-14 08:09:09 +00:00
Stanislav Shwartsman
fd15b61d94 keep def of YMM/ZMM register even if AVX or EVEX are not compiled in and let reading/writing them to MEM 2018-04-04 19:31:56 +00:00
Stanislav Shwartsman
773f1b7e42 cleanup return value of all instruction handlers 2018-02-16 07:57:32 +00:00
Stanislav Shwartsman
2bca4cc310 improve debug print for SPP access 2018-01-27 21:25:46 +00:00
Stanislav Shwartsman
afc2ee6bfd Implemented SPP: EPT-Based Subpage Protection. Cleaned code duplication between FXSAVE/FXRSTORE and XSAVE/XRSTOR (save/restore of SSE code is the same) 2018-01-27 21:20:33 +00:00
Stanislav Shwartsman
ca034f0642 fixed disasm of sse insertps instruction 2017-12-21 18:18:10 +00:00
Stanislav Shwartsman
e086f7ba19 split INSERTPS opcode to reg and mem forms 2017-12-19 19:25:40 +00:00
Stanislav Shwartsman
5dc5e01a12 disasm fixes and reorg of pinsr* opcodes 2017-12-16 18:34:20 +00:00
Stanislav Shwartsman
50a799ea11 split handlers for PINSRD/Q opcodes. fix disasm for MULX instruction 2017-12-13 20:18:59 +00:00
Stanislav Shwartsman
8a311515dd correctly decode VPEXTRB/W/D/Q - these opcodes allowed to be with VEX.L=0 only 
fixed disasm module compilation with no AVX enabled
remove duplicate opcode handlers
 2017-12-13 19:51:25 +00:00
Stanislav Shwartsman
596b3b6eb8 reduce CPU dependencies from fetchdecode module 2017-11-25 20:20:34 +00:00
Stanislav Shwartsman
8261a91ce9 implemented GFNI instructions 2017-10-21 19:57:12 +00:00
Stanislav Shwartsman
77a62a4dcd implemented (experimental, still untested) AVX512 VBMI2 extensions 2017-10-20 18:38:15 +00:00
Stanislav Shwartsman
ba1e5bbffa fixed accidentially broken XMM versions of AES instrructions 2017-10-19 20:25:05 +00:00
Stanislav Shwartsman
15ba88c195 implemented VAES/VPCLMULDQ instructions - VEX/EVEX extensions of AES/PCLMULQDQ 2017-10-19 19:12:55 +00:00
Stanislav Shwartsman
ac442009aa lazy flags code small refactoring 2017-10-15 22:01:32 +00:00
Stanislav Shwartsman
944f37b1f2 implemented AVX-512 BITALG instructions/bugfix for VPOPCNT instructions 2017-10-15 20:33:19 +00:00
Stanislav Shwartsman
0d190eec8e implemented AVX-512 VNNI instructions 2017-10-15 19:17:07 +00:00
Stanislav Shwartsman
1abfcd39ff implement FOPCODE and FDP deprecation CPU features 2017-05-05 20:56:13 +00:00
Stanislav Shwartsman
097310cd00 fixed integer overflow while computing shift flags, avoid using bx_bool while working with flags for more robust code 2017-03-30 21:53:39 +00:00
Stanislav Shwartsman
a673612784 fixed permission checks performed by CLFLUSH/CLFLUSHOPT/MONITOR* instructions 2017-03-28 18:52:53 +00:00
Stanislav Shwartsman
2b79061127 Implemented MONITORX/MWAITX instructions (AMD), enabled in Ryzen CPU model 2017-03-26 19:14:15 +00:00
Stanislav Shwartsman
411ea954b4 implemented CLZERO instruction from AMD Ryzen CPU 2017-03-25 20:12:31 +00:00
Stanislav Shwartsman
15d9b068a3 fix msvc warnings 2017-03-17 17:35:15 +00:00
Stanislav Shwartsman
3a033fa6db implemented xsaves/xrstors extensions (supported by Intel Skylake core and AMD Ryzen) 2017-03-15 21:44:15 +00:00
Stanislav Shwartsman
9bd99a604f implemented recently announced AVX-512 extension VPOPCNT 2016-12-17 13:47:45 +00:00
Stanislav Shwartsman
7a34f00f99 extracted fetchdecode into separated folder under cpu and also out of BX_CPU_C class into stand-alone module. Next step: wrap it up nicely and define clear interace to CPU model to minimize dependencies. Ideally I need fetchdecode to not include CPU at all 2016-06-12 21:23:48 +00:00
Stanislav Shwartsman
8824539630 fix code duplication in segload instr emulation 2016-06-01 20:11:54 +00:00
Stanislav Shwartsman
e24c7e403a take a funtion from BX_CPU_C:: into fetchdecode.cc standalone function 2016-04-30 19:13:15 +00:00
Stanislav Shwartsman
793ceb0d8c fix massive code dupliction between disasm, debugger and cpu by introducing new cpu decoder.h header 2016-04-29 21:01:28 +00:00
Stanislav Shwartsman
cc49b504b3 fix small issue on the way to Bochs decoder separation into stand-alone module 2016-04-26 12:46:44 +00:00
Stanislav Shwartsman
adc143684b implemented Intel architecture extensions published in recently published SDM 058: 
! Implemented UMIP: User Mode Instruction Prevention (don't allow execution of SLDT/SIDT/SGDT/STR/SMSW with CPL>0)
! Implemented RDPID instruction

Bugfixes in RDPKRU/WRPKRU instructions implementation (Protection Keys feature)
 2016-04-15 11:35:32 +00:00
Stanislav Shwartsman
e4832af5ab clean pkeys when not enabled to avoid side-effects 2016-03-19 21:15:56 +00:00
Stanislav Shwartsman
bcb36e81fa experimental implementation of protection keys paging extension published in SDM rev054. to enable configure with --enable-protection-keys 2016-03-02 20:44:42 +00:00