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382 Commits

Author SHA1 Message Date
Stanislav Shwartsman
7f8429c643 fix code duplication in fetchdecode modules 2013-11-20 16:00:24 +00:00
Stanislav Shwartsman
3be7e5884b added lock prefix used info into bx_Instriction_c and use it in disasm 2013-11-08 21:43:21 +00:00
Stanislav Shwartsman
39f2f172b5 fixed PAUSE/NOP decoding bug in prev commit 2013-10-16 05:46:57 +00:00
Stanislav Shwartsman
8bcc8cf073 split PREFETCH opcode to Group16 for better disasm of bxInstruction_c 2013-10-15 21:21:28 +00:00
Stanislav Shwartsman
940c2a1c8e fixes for disasm 2013-10-15 17:19:18 +00:00
Stanislav Shwartsman
9fb7384e6b finish sse tables cleanup in disasm and fetchdecode 2013-10-11 20:09:51 +00:00
Stanislav Shwartsman
34025e469f resolve aliases after actually decoding base instr 2013-10-11 05:54:18 +00:00
Stanislav Shwartsman
46e36b463b size-optimization for SSE opcode tables 2013-10-10 20:21:15 +00:00
Stanislav Shwartsman
0b2e533a55 more avx512 instructions done 2013-10-09 19:45:36 +00:00
Stanislav Shwartsman
09254eb474 avx512 implementation fixes and next steps 2013-10-08 18:31:18 +00:00
Stanislav Shwartsman
5724013e7d updates to AVX512 decoding and CPUID 2013-10-07 20:39:34 +00:00
Stanislav Shwartsman
cb0eee9456 disasm fixes 2013-10-07 19:02:53 +00:00
Stanislav Shwartsman
059769e2a6 disasm bug fixes 2013-10-06 20:42:13 +00:00
Stanislav Shwartsman
d4bfbffdbb disasm fixes 2013-10-05 08:34:09 +00:00
Stanislav Shwartsman
ba1249ed15 disasm fixes 2013-10-04 17:26:56 +00:00
Stanislav Shwartsman
85b0402668 fixes for disasm 2013-10-02 19:23:34 +00:00
Stanislav Shwartsman
fd383435f0 - Initial code for bx_Instruction_c disassembler which (together with Bochs decoder) will replace Bochs disasm module someday (very soon). 
The code already knows to disasm most of the opcodes with their operands.

- Split according to OSIZE opcodes RDFSBASE/WRFSBASE / RDGSBASE/WRGSBASE both for disasm and performance

- Minimize amount of opcode forms in ia_opcodes.h again.
  For example Udq means the same as Wdq but with no memory form.
 2013-09-30 19:01:42 +00:00
Stanislav Shwartsman
fa06b26c88 Make possible to deliver instruction name for disasm directly from bx_ia_opcode_name (some opcodes were renamed). 
Fixed bug in stack optimization in 64-bit mode (should result in some speedup)
ia_opcode.h - eliminate some OP_M cases when they actually meant "value of specific type in the memory"
example: "MOVBE Md, Gd" actually means "MOVBE Ed, Gd"which just not have reg/reg form.
 2013-09-26 18:54:32 +00:00
Stanislav Shwartsman
839b841c38 added register type to register source information in decoder 2013-09-24 09:50:25 +00:00
Stanislav Shwartsman
ff79cbd596 Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm) 
The end goal will be also merging of disasm and cpu decoder to one module and remove the disasm.

Two bug fixes on the way:
TBM: fixed 64-bit TBM instructions with memory access (did 32-bit load instead of 64-bit)
BMI2: fixed operands order for PEXT/PDEP instructions
AVX2: fixed gather instruction decoding bug from decoder alias commit
 2013-09-24 05:21:00 +00:00
Stanislav Shwartsman
404b8b1475 move end of trace indication to separate 'flags' field of bx_ia_opcode. this saves a lot of code duplication and simplifies the decode tables. also on the way found missing SVM opcodes that missed 'end of trace' mark 2013-09-21 18:58:01 +00:00
Stanislav Shwartsman
2526282ed9 small additions for avx512 2013-09-20 18:27:33 +00:00
Stanislav Shwartsman
8b3a0acde9 implement first EVEX instructions - VADDPS/PD/SS/SD 2013-09-19 18:31:30 +00:00
Stanislav Shwartsman
8e71a86542 seve vex prefix value to the indication of vex prefix used 2013-09-18 18:01:48 +00:00
Stanislav Shwartsman
aa25c1db6a name convention change - search and replace 2013-09-17 17:34:20 +00:00
Stanislav Shwartsman
0cb0acc30f added evex decode tables - next step to populate them :) 2013-09-15 20:48:39 +00:00
Stanislav Shwartsman
7297323c69 First step of AVX512 support implementation (simplest) 
decode and implement KMASK manipulation instructions
disasm: coming soon
 2013-09-08 19:19:16 +00:00
Stanislav Shwartsman
a6b85d9443 compress xop tables for vex.l - smaller binary size 2013-09-06 18:56:46 +00:00
Stanislav Shwartsman
2c9cf33b2f update (c) for few files 2013-09-05 18:37:10 +00:00
Stanislav Shwartsman
69f947cef2 fixes and small optimizations for avx and xop decoding 2013-09-05 18:29:50 +00:00
Stanislav Shwartsman
f36364bc65 it doesn't matter if it was vex or xop ... 2013-09-05 17:52:47 +00:00
Stanislav Shwartsman
2f957bf142 re-arrange AVX/XOP table to avoid redundant multiplication in decode. TODO: compress the tables 2x using aliases 2013-09-04 18:36:01 +00:00
Stanislav Shwartsman
81affbe328 fixed incorrect lock prefix detection 2013-08-30 20:08:04 +00:00
Stanislav Shwartsman
59c65151f5 various fixes 2013-08-29 19:43:15 +00:00
Stanislav Shwartsman
7e2ab5ca81 decode simplification for AMD XOP prefix 2013-08-28 19:56:19 +00:00
Stanislav Shwartsman
5fe5bf1ed6 fixed alias typo corrupting avx opcodes 2013-08-27 19:45:31 +00:00
Stanislav Shwartsman
c5f72033ad correct vzeroupper opcode 2013-08-27 06:57:48 +00:00
Stanislav Shwartsman
735154a755 oops, typo bug in prev commit 2013-08-24 19:46:04 +00:00
Stanislav Shwartsman
65e6760915 small decode optimization 2013-08-24 19:29:43 +00:00
Stanislav Shwartsman
748a0da712 one more step in the way towards avx-512 which have more vector registers 2013-08-24 12:12:10 +00:00
Stanislav Shwartsman
3a7e336cb6 more opcode alias - now VEX.W alias 2013-08-21 18:45:36 +00:00
Stanislav Shwartsman
115ec37a4c make decoder tables smaller using decode aliases 2013-08-21 04:52:49 +00:00
Stanislav Shwartsman
7005afd3a8 clean up BxRepeatable attribute - not needed anymore after VL AVX field moved to new location 2013-07-26 15:42:49 +00:00
Stanislav Shwartsman
2dbe81db51 first infrastructure changes to support EVEX prefix and AVX-512 extensions recently published by Intel 2013-07-26 12:50:56 +00:00
Stanislav Shwartsman
685e0091b4 fixed decoding of RDRAND/RDSEED with 0x66 prefix 2012-12-27 19:31:21 +00:00
Stanislav Shwartsman
9b65cae026 make WRMSR end-of-trace instruction 2012-10-25 16:49:22 +00:00
Stanislav Shwartsman
2638c1136a Add RDRAND/RDSEED instructions support (+ disasm) 
Of course no true random numbers will be generated - use standard "C" rand() function as stub.
In future it will be possible to improve (using another random generator) or even use real rdrand/rdseed intrinsics
 2012-10-09 15:16:48 +00:00
Stanislav Shwartsman
74f5bb1934 WBINVD not necessary havw to flush ICACHE 2012-09-21 08:55:10 +00:00
Stanislav Shwartsman
8044a2bda6 rename i->execute field in the instruction 
move victim cache lookup into cache lookup so traces could be linked with victim cache hits directly
 2012-09-04 15:45:05 +00:00
Stanislav Shwartsman
295e3ab8db fixed compilation warning 2012-09-02 18:38:04 +00:00