Commit Graph

158 Commits

Author SHA1 Message Date
Rudolf Cornelissen
c80ea54975 intel_extreme: PLLs post skylake work differently again. Refclk update. 2021-12-05 16:56:15 +00:00
Rudolf Cornelissen
d60c7e010c intel_extreme: for gen9.5 added new portF to DDI scan. add ID dump in kerneldriver. 2021-12-05 12:47:05 +00:00
Rudolf Cornelissen
77b2dd17df intel_extreme: added DDI link colordepth detection, may fix ticket #17439 2021-12-04 23:24:50 +00:00
Jérôme Duval
3fedf64872 intel_extreme: enable KabyLake
Change-Id: I81d04fdf8305efcc9250cfb975dd3466ebcb4058
Reviewed-on: https://review.haiku-os.org/c/haiku/+/4740
Reviewed-by: Jérôme Duval <jerome.duval@gmail.com>
2021-11-30 08:06:56 +00:00
Kacper Kasper
66aae93087 intel_extreme: enable CoffeeLake
Change-Id: Id73c88d0815259fa7a8027f757ac430818492b1e
Reviewed-on: https://review.haiku-os.org/c/haiku/+/4739
Reviewed-by: Jérôme Duval <jerome.duval@gmail.com>
2021-11-30 08:06:56 +00:00
Kacper Kasper
fe9ab0f353 intel_gart: add support for Gen8+ GPUs
Change-Id: I8b84e278f33542c359fc0d783f571e06ebc89b2a
Reviewed-on: https://review.haiku-os.org/c/haiku/+/4737
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Rudolf Cornelissen <rudhaiku@gmail.com>
2021-11-29 18:14:21 +00:00
Rudolf Cornelissen
03ed104900 intel_extreme: enabled all known skylake gfx cards since they are pgm'd now 2021-11-26 23:52:15 +00:00
Rudolf Cornelissen
39e05c7d01 intel_extreme: skylake PLL works, all outputs fully functional. 2021-11-25 22:41:48 +00:00
Rudolf Cornelissen
efde34c2fc intel_extreme: add haswell/skylake PLL calcs, no functional change yet. 2021-11-22 11:14:36 +00:00
Rudolf Cornelissen
ae7d733d42 intel_extreme: skylake/DDI. all displays can set resolution now, no refresh on digital panels yet (DPLL still missing) 2021-11-16 00:39:49 +00:00
Rudolf Cornelissen
0eb2bf0e66 intel_extreme: skylake/DDI improvements. no resolution changing possible yet (missing DPLL code yet) 2021-11-14 23:16:44 +00:00
Rudolf Cornelissen
661732341f intel_extreme: haswell and skylake DDI EDID support added, modesetting not finished yet. 2021-11-02 20:04:37 +00:00
Adrien Destugues
4492fde7bf intel_extreme: reduce use of display_mode where display_timing is enough
In most cases we don't need to use the complete display_mode struct and
we just need the timings. This will avoid future confusion between the
virtual width/height and the actual display timings, if we implement
scrolling someday.

Change-Id: I6c4430b84130b956a47ea0a01afb0843f5a34fd2
Reviewed-on: https://review.haiku-os.org/c/haiku/+/4665
Reviewed-by: waddlesplash <waddlesplash@gmail.com>
2021-10-27 14:33:46 +00:00
Rudolf Cornelissen
994794f2d4 intel extreme: skylake sets color, base and address, no resolution and refresh yet 2021-10-23 17:13:43 +00:00
Rudolf Cornelissen
fe8f9e2326 intel_extreme: set B_SCROLL, share current mode. Cloning and BWindowScreen now work OK. 2021-09-27 10:19:43 +00:00
Rudolf Cornelissen
96c8657d24 intel_extreme: fix haswell virt display scroll/pan, ticket #17261 2021-09-17 23:46:00 +00:00
Rudolf Cornelissen
3334d6fba1 intel_extreme: gen4 displayport now sets modes, dualhead clone works. 2021-07-02 14:19:58 +00:00
Rudolf Cornelissen
b3bafaf695 intel_extreme: displayport now scales to BIOS set mode. 2021-06-30 00:47:10 +00:00
Rudolf Cornelissen
13a4e5a056 intel_extreme: haswell+ has DDI, no DP, so block scanning that for screens. 2021-06-27 17:47:04 +00:00
Rudolf Cornelissen
def51fb910 intel_extreme: don't pgm pipes, follow BIOS for now. Two screens on now i.e. 2021-06-25 10:40:08 +00:00
Rudolf Cornelissen
16ea5aac34 intel driver: added panelfitter pgmming. 2021-06-14 22:49:31 +00:00
Rudolf Cornelissen
aca9888e37 Intel_extreme: fixed hrev55115 regression and added FDI data/link M/N programming. 2021-06-08 09:30:38 +00:00
Rudolf Cornelissen
c7d83a174c Intel_extreme: fixed DPLL pgming (Sandy+), prevent black display by not killing PIPE (Ivy+). Chkd GMA(Q33G/Q45) OK. Added defines. 2021-05-29 08:41:32 +00:00
Jérôme Duval
bed01fe356 AreaKeeper.h: move to headers/private/kernel
Change-Id: I9ae2b9a6243809a618c0520a26e064ce3c5be2b4
Reviewed-on: https://review.haiku-os.org/c/haiku/+/2410
Reviewed-by: waddlesplash <waddlesplash@gmail.com>
2020-03-23 16:38:01 +00:00
Adrien Destugues
22ec64553f intel_extreme: some minor fixes
- Cleanup HEAD_MODE constants. These should be completely removed, now
  that we have a proper notion of pipes and displays. But the DPMS code
  still uses them, for now.
- Fix the ie_pipe command where width and height were swapped and
  missing a +1 to show the actual videomode values
2020-03-13 15:42:03 +01:00
Adrien Destugues
168aff90a7 intel_extreme: program the DPLL_SEL register on SandyBridge
We need to assign PLLs to pipes and transcoders. The assignments on
previous generations were fixed, but now it's up to us to set it up.

Do the simplest thing for now: assign PLL1 to pipe A and PLL2 to pipe B.
2020-03-08 16:01:43 +01:00
Adrien Destugues
ec4e9ea8bc intel_extreme: remove unhandled generation defines
- 7xx (1st gen) has no driver in Haiku or is handled by the intel_810 driver
- PowerVR has no driver in Haiku

So there is no point in having those in the intel_extreme driver.

While I'm at it, fix the video timing/resolution constraints for
sanitize_video_mode.
2020-01-27 13:58:52 +01:00
Adrien Destugues
1808b553a2 intel_extreme: do not reprogram transcoded/output mapping on ibex point
Another try to fix #15628
2020-01-19 11:04:31 +01:00
Adrien Destugues
2beddbfd46 intel_extreme: fix pipe and plane size registers
- The name for the registers were swapped
- The width and height were also swapped in one of them
- Remove some old #if 0 code that touched these registers but has been
  disabled for a while.
2020-01-05 10:11:37 +01:00
Adrien Destugues
abcbfac601 intel_extreme: use the panel fitter for generation 4 devices
LVDS panels must really be driven at their native resolution, otherwise
they will simply not work. This means we should basically never touch
the video timings on that side. We need to only set the source size in
the pipe configuration, and let the panel fitter figure out the scaling.

On my G45 laptop, this allows me to use non-native resolutions on the
laptop display. This also means when booting with a VGA display
connected, I do get a valid display on the internal panel (using the VGA
resolution). VGA still gets "out of range", so we're still not setting
up something there.

If I switch to VGA display in the BIOS, I get a working picture there
and garbage on the internal display, which is progress (before I would
get a black screen on the internal display)

Fixes #12723.
2020-01-05 10:11:37 +01:00
Alexander von Gluck IV
7d95ab67ad intel_extreme: Update PCH mask to match new bits
* Missed in 87628f17eb
2018-06-12 14:20:34 -05:00
Alexander von Gluck IV
87628f17eb intel_extreme: Add additional more recent PCH devices
Change-Id: Ib9f7dc187300c9f746bca9fd7f721c1954f5be44
2018-06-11 20:34:14 -05:00
Augustin Cavalier
52d1e93353 Revert "intel_extreme: Broadwell is really Gen7(.5), not 8."
This reverts commit 4f059c1fc5.

From discussion on the mailing list, it seems I was correct the first time
and Broadwell is Gen8. The confusion comes from the SER5/SOC distinction,
which is not in the Linux driver, and I still don't know which one it really
belongs in.
2018-06-05 21:07:59 -04:00
Augustin Cavalier
4f059c1fc5 intel_extreme: Broadwell is really Gen7(.5), not 8. 2018-06-05 17:27:45 +00:00
Adrien Destugues
8ddec194c6 intel_extreme: backlight control on pre-PCH devices
Thanks to oco for letting me test this on his old laptop.
2017-11-23 23:59:39 +01:00
Augustin Cavalier
164e4f8de4 intel_extreme: Beginnings of Broadwell support.
At present, does not work (it fails to properly set up interrupts,
resulting in thousands of unhandled ones which all but grinds the system
to a halt) but this at least is some progress.
2017-11-21 23:37:18 +00:00
Adrien Destugues
3a2b67b5ae Support for configuring screen backlight
Accelerant interface:
Introduce new hooks B_SET_BRIGHTNESS and B_GET_BRIGHTNESS. Brightness is
a float in the 0..1 range.

App_server:
Forward brightness things between BScreen and the accelerant.

intel_extreme:
Implement the hooks. Note that this only works for laptop panels, but
the driver will pretend to support it in other cases as well.

Screen preferences:
If the accelerant supports the B_GET_BRIGHTNESS hook, allow to set
brightness with a slider. Otherwise, the slidere is hidden and these
changes aren't visible.
2017-11-21 09:12:18 +01:00
Adrien Destugues
187ad82a62 intel_extreme: fix wait_for_vblank on SandyBridge
There was some mixup with the interrupt registers, still:
- The driver uses 16-bit read/write, but on SandyBridge the register is
  32 bits
- There is a global interrupt enable bit, which must be set to unmask
  everything else
- The bits for vblank interrupt are not the same on SNB and later PCH
  based devices, and the code mixed the two.

Move the computation of the interrupt bits to an helper function, and
use it everywhere to make sure we always use the right bits.
2016-08-26 21:45:38 +02:00
Adrien Destugues
adc0f76e64 More SandyBridge fixes and cleanups
Modesetting
===========

My previous hack was setting the transcoder registers, instead of the
display ones. Do that the way it is designed in the driver instead:

- If there is a transcoder, set its registers, but do not set the
display timings. The display will remain set at its native (and only)
resolution, and panel fitting will adjust the output of the transcoder
to match.
- If there is no transcoder, set the display registers directly to the
native resolution, as it was done on previous generation devices.
- fPipeOffset hacks no longer needed

DPMS
====

It seems the panel control register is not readable on PCH? Anyway, the
code would loop forever waiting for the bit to become unset when turning
the display off. Waiting seems to not be needed, so just remove it as
well as the "unlock" bit, which does not work for me and results in a
black screen.

Remaining hacks
===============

I still need to force HEAD_MODE_A_ANALOG to get output on pipe B (LVDS
display) working. I suspect something is common to the two pipes or not
allocated to the right one.

This version will have less side effects on other generations and help
with getting things to work on SandyBridge and possibly later devices.
Please test and report.
2016-08-25 23:17:12 +02:00
Adrien Destugues
bb4190f050 Fix SandyBridge support.
This reverts commit 4f2b258c32.
This reverts commit c86f3dba23.
This reverts commit 61fbdb0667.
This reverts commit b3f14fb7c7.
2016-08-21 16:54:03 +02:00
Alexander von Gluck IV
95b6439eec intel_extreme: Implement Snb PCH FDI link training 2016-07-29 17:49:59 -05:00
Alexander von Gluck IV
c0d4def4e4 intel_extreme: Implement Ilk PCH FDI link training
* IronLake tested and FDI says it trains successfully
* Still no LVDS video on Ilk
2016-07-29 16:04:40 -05:00
Alexander von Gluck IV
f6c32ce310 intel_extreme: Set FDI PLL RX lane count when enabling 2016-07-20 00:25:38 -05:00
Alexander von Gluck IV
a933bb4cbc intel_extreme: IronLake reference clock activation 2016-07-17 15:25:08 -05:00
Alexander von Gluck IV
92e254d047 intel_extreme: Improve PCH detection
* Detect PCH model based on ISA bridge and save
  into shared info for later use.
* On CougarPoint PCH systems, assign pipes via
  special CPT registers
* Drop HasPlatformControlHub as PCH should be
  based on more than just generation.
2016-07-10 21:02:01 -05:00
Alexander von Gluck IV
8fe5054828 intel_extreme: Extend DDI port probing to A-E
* The Linux code made this a bit hard to figure out via
  complex define functions, however there can be up to
  5 DDI ports (A-E)
2016-05-08 15:40:57 -05:00
Alexander von Gluck IV
8d1cb54aac intel_extreme: Add in some code for the lakes (unused) 2016-04-22 22:41:52 -05:00
Alexander von Gluck IV
ca95e9dad9 intel_extreme: Add initial work for DDI ports 2016-03-15 18:12:28 -05:00
Alexander von Gluck IV
3d1bd895ad intel_extreme: Properly use VBIOS panel mode
* Move current_mode into the accelerant as the
  driver doesn't care.
* Record panel_mode in driver and present to accelerant
* eDP, if no EDID and mobile, leave edid incomplete.
  Mode set should notice that and fall back to panel_mode
2016-03-11 18:20:28 -06:00
Alexander von Gluck IV
721ba9af43 intel_extreme: Clean up DisplayPort Port class
* DisplayPort != DigitalPort
* i2c needs wrapped in DP AUX transaction code
* Mode-setting comes with DP link training as well
* We need to try and share DP code with radeon_hd
2016-02-23 14:10:14 -06:00