intel_extreme: add haswell/skylake PLL calcs, no functional change yet.
This commit is contained in:
Rudolf Cornelissen
parent
4106e3f146
commit
efde34c2fc
@ -512,7 +512,7 @@ struct intel_free_graphics_memory {
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#define LVDS_18BIT_DITHER (1UL << 25)
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#define LVDS_PORT_EN (1UL << 31)
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// PLL flags
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// PLL flags (pre-DDI)
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#define DISPLAY_PLL_ENABLED (1UL << 31)
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#define DISPLAY_PLL_2X_CLOCK (1UL << 30)
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#define DISPLAY_PLL_SYNC_LOCK_ENABLED (1UL << 29)
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@ -540,6 +540,17 @@ struct intel_free_graphics_memory {
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#define DISPLAY_PLL_M2_DIVISOR_SHIFT 0
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#define DISPLAY_PLL_PULSE_PHASE_SHIFT 9
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// Skylake PLLs
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#define SKL_DPLL1_CFGCR1 (0xc040 | REGS_NORTH_PIPE_AND_PORT)
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#define SKL_DPLL1_CFGCR2 (0xc044 | REGS_NORTH_PIPE_AND_PORT)
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#define SKL_DPLL2_CFGCR1 (0xc048 | REGS_NORTH_PIPE_AND_PORT)
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#define SKL_DPLL2_CFGCR2 (0xc04c | REGS_NORTH_PIPE_AND_PORT)
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#define SKL_DPLL3_CFGCR1 (0xc050 | REGS_NORTH_PIPE_AND_PORT)
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#define SKL_DPLL3_CFGCR2 (0xc054 | REGS_NORTH_PIPE_AND_PORT)
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#define SKL_DPLL_CTRL1 (0xc058 | REGS_NORTH_PIPE_AND_PORT)
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#define SKL_DPLL_CTRL2 (0xc05c | REGS_NORTH_PIPE_AND_PORT)
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#define SKL_DPLL_STATUS (0xc060 | REGS_NORTH_PIPE_AND_PORT)
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// display
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#define INTEL_DISPLAY_OFFSET 0x1000
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@ -461,6 +461,17 @@ Pipe::ConfigureClocks(const pll_divisors& divisors, uint32 pixelClock,
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}
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}
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void
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Pipe::ConfigureClocksSKL(const skl_wrpll_params& wrpll_params, uint32 pixelClock,
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uint32 extraFlags)
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{
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CALLED();
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TRACE("Skylake DPLL_CTRL1: 0x%" B_PRIx32 "\n", read32(SKL_DPLL_CTRL1));
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TRACE("Skylake DPLL_CTRL2: 0x%" B_PRIx32 "\n", read32(SKL_DPLL_CTRL2));
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TRACE("Skylake DPLL_STATUS: 0x%" B_PRIx32 "\n", read32(SKL_DPLL_STATUS));
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}
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void
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Pipe::Enable(bool enable)
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{
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@ -47,6 +47,10 @@ public:
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const pll_divisors& divisors,
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uint32 pixelClock,
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uint32 extraFlags);
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void ConfigureClocksSKL(
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const skl_wrpll_params& wrpll_params,
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uint32 pixelClock,
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uint32 extraFlags);
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// access to the various parts of the pipe
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::FDILink* FDI()
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@ -1524,18 +1524,32 @@ DigitalDisplayInterface::SetDisplayMode(display_mode* target, uint32 colorMode)
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}
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}
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pll_divisors divisors;
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compute_pll_divisors(&target->timing, &divisors, false);
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uint32 extraPLLFlags = 0;
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if (gInfo->shared_info->device_type.Generation() >= 3)
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extraPLLFlags |= DISPLAY_PLL_MODE_NORMAL | DISPLAY_PLL_2X_CLOCK;
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// Program general pipe config
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fPipe->Configure(target);
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//pll_divisors divisors;
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//compute_pll_divisors(&target->timing, &divisors, false);
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//uint32 extraPLLFlags = 0;
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//if (gInfo->shared_info->device_type.Generation() >= 3)
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// extraPLLFlags |= DISPLAY_PLL_MODE_NORMAL | DISPLAY_PLL_2X_CLOCK;
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// Program pipe PLL's
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fPipe->ConfigureClocks(divisors, target->timing.pixel_clock, extraPLLFlags);
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//fPipe->ConfigureClocks(divisors, target->timing.pixel_clock, extraPLLFlags);
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if (gInfo->shared_info->device_type.Generation() <= 8) {
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unsigned int r2_out, n2_out, p_out;
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hsw_ddi_calculate_wrpll(
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target->timing.pixel_clock * 1000 /* in Hz */,
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&r2_out, &n2_out, &p_out);
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} else {
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skl_wrpll_params wrpll_params;
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skl_ddi_calculate_wrpll(
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target->timing.pixel_clock * 1000 /* in Hz */,
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gInfo->shared_info->pll_info.reference_frequency,//fixme Hz? kHz?
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&wrpll_params);
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fPipe->ConfigureClocksSKL(wrpll_params, target->timing.pixel_clock, 0);
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}
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// Program target display mode
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fPipe->ConfigureTimings(target);
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@ -552,3 +552,485 @@ refclk_activate_ilk(bool hasPanel)
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}
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}
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//excerpt (plus modifications) from intel_dpll_mgr.c:
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/*
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* Copyright © 2006-2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#define LC_FREQ 2700
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#define LC_FREQ_2K (uint64)(LC_FREQ * 2000)
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#define P_MIN 2
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#define P_MAX 64
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#define P_INC 2
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/* Constraints for PLL good behavior */
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#define REF_MIN 48
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#define REF_MAX 400
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#define VCO_MIN 2400
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#define VCO_MAX 4800
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struct hsw_wrpll_rnp {
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unsigned p, n2, r2;
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};
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static unsigned hsw_wrpll_get_budget_for_freq(int clock)
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{
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unsigned budget;
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switch (clock) {
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case 25175000:
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case 25200000:
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case 27000000:
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case 27027000:
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case 37762500:
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case 37800000:
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case 40500000:
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case 40541000:
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case 54000000:
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case 54054000:
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case 59341000:
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case 59400000:
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case 72000000:
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case 74176000:
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case 74250000:
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case 81000000:
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case 81081000:
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case 89012000:
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case 89100000:
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case 108000000:
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case 108108000:
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case 111264000:
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case 111375000:
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case 148352000:
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case 148500000:
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case 162000000:
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case 162162000:
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case 222525000:
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case 222750000:
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case 296703000:
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case 297000000:
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budget = 0;
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break;
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case 233500000:
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case 245250000:
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case 247750000:
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case 253250000:
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case 298000000:
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budget = 1500;
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break;
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case 169128000:
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case 169500000:
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case 179500000:
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case 202000000:
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budget = 2000;
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break;
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case 256250000:
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case 262500000:
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case 270000000:
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case 272500000:
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case 273750000:
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case 280750000:
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case 281250000:
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case 286000000:
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case 291750000:
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budget = 4000;
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break;
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case 267250000:
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case 268500000:
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budget = 5000;
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break;
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default:
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budget = 1000;
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break;
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}
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return budget;
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}
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static void hsw_wrpll_update_rnp(uint64 freq2k, unsigned int budget,
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unsigned int r2, unsigned int n2,
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unsigned int p,
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struct hsw_wrpll_rnp *best)
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{
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uint64 a, b, c, d, diff, diff_best;
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/* No best (r,n,p) yet */
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if (best->p == 0) {
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best->p = p;
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best->n2 = n2;
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best->r2 = r2;
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return;
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}
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/*
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* Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
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* freq2k.
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*
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* delta = 1e6 *
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* abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
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* freq2k;
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*
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* and we would like delta <= budget.
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*
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* If the discrepancy is above the PPM-based budget, always prefer to
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* improve upon the previous solution. However, if you're within the
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* budget, try to maximize Ref * VCO, that is N / (P * R^2).
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*/
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a = freq2k * budget * p * r2;
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b = freq2k * budget * best->p * best->r2;
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diff = abs((uint64)freq2k * p * r2 - LC_FREQ_2K * n2);
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diff_best = abs((uint64)freq2k * best->p * best->r2 -
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LC_FREQ_2K * best->n2);
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c = 1000000 * diff;
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d = 1000000 * diff_best;
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if (a < c && b < d) {
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/* If both are above the budget, pick the closer */
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if (best->p * best->r2 * diff < p * r2 * diff_best) {
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best->p = p;
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best->n2 = n2;
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best->r2 = r2;
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}
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} else if (a >= c && b < d) {
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/* If A is below the threshold but B is above it? Update. */
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best->p = p;
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best->n2 = n2;
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best->r2 = r2;
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} else if (a >= c && b >= d) {
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/* Both are below the limit, so pick the higher n2/(r2*r2) */
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if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
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best->p = p;
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best->n2 = n2;
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best->r2 = r2;
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}
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}
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/* Otherwise a < c && b >= d, do nothing */
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}
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void
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hsw_ddi_calculate_wrpll(int clock /* in Hz */,
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unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
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{
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uint64 freq2k;
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unsigned p, n2, r2;
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struct hsw_wrpll_rnp best = { 0, 0, 0 };
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unsigned budget;
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freq2k = clock / 100;
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budget = hsw_wrpll_get_budget_for_freq(clock);
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/* Special case handling for 540 pixel clock: bypass WR PLL entirely
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* and directly pass the LC PLL to it. */
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if (freq2k == 5400000) {
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*n2_out = 2;
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*p_out = 1;
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*r2_out = 2;
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return;
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}
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/*
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* Ref = LC_FREQ / R, where Ref is the actual reference input seen by
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* the WR PLL.
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*
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* We want R so that REF_MIN <= Ref <= REF_MAX.
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* Injecting R2 = 2 * R gives:
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* REF_MAX * r2 > LC_FREQ * 2 and
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* REF_MIN * r2 < LC_FREQ * 2
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*
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* Which means the desired boundaries for r2 are:
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* LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
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*
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*/
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for (r2 = LC_FREQ * 2 / REF_MAX + 1;
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r2 <= LC_FREQ * 2 / REF_MIN;
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r2++) {
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/*
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* VCO = N * Ref, that is: VCO = N * LC_FREQ / R
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*
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* Once again we want VCO_MIN <= VCO <= VCO_MAX.
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* Injecting R2 = 2 * R and N2 = 2 * N, we get:
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* VCO_MAX * r2 > n2 * LC_FREQ and
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* VCO_MIN * r2 < n2 * LC_FREQ)
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*
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* Which means the desired boundaries for n2 are:
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* VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
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*/
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for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
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n2 <= VCO_MAX * r2 / LC_FREQ;
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n2++) {
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for (p = P_MIN; p <= P_MAX; p += P_INC)
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hsw_wrpll_update_rnp(freq2k, budget,
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r2, n2, p, &best);
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}
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}
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*n2_out = best.n2;
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*p_out = best.p;
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*r2_out = best.r2;
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}
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struct skl_wrpll_context {
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uint64 min_deviation; /* current minimal deviation */
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uint64 central_freq; /* chosen central freq */
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uint64 dco_freq; /* chosen dco freq */
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unsigned int p; /* chosen divider */
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};
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/* DCO freq must be within +1%/-6% of the DCO central freq */
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#define SKL_DCO_MAX_PDEVIATION 100
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#define SKL_DCO_MAX_NDEVIATION 600
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static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
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uint64 central_freq,
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uint64 dco_freq,
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unsigned int divider)
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{
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uint64 deviation;
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deviation = ((uint64)10000 * abs(dco_freq - central_freq)
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/ (uint64)central_freq);
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/* positive deviation */
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if (dco_freq >= central_freq) {
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if (deviation < SKL_DCO_MAX_PDEVIATION &&
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deviation < ctx->min_deviation) {
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ctx->min_deviation = deviation;
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ctx->central_freq = central_freq;
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ctx->dco_freq = dco_freq;
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ctx->p = divider;
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}
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/* negative deviation */
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} else if (deviation < SKL_DCO_MAX_NDEVIATION &&
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deviation < ctx->min_deviation) {
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ctx->min_deviation = deviation;
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ctx->central_freq = central_freq;
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ctx->dco_freq = dco_freq;
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ctx->p = divider;
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}
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}
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static void skl_wrpll_get_multipliers(unsigned int p,
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unsigned int *p0 /* out */,
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unsigned int *p1 /* out */,
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unsigned int *p2 /* out */)
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{
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/* even dividers */
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if (p % 2 == 0) {
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unsigned int half = p / 2;
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if (half == 1 || half == 2 || half == 3 || half == 5) {
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*p0 = 2;
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*p1 = 1;
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*p2 = half;
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} else if (half % 2 == 0) {
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*p0 = 2;
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*p1 = half / 2;
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*p2 = 2;
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} else if (half % 3 == 0) {
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*p0 = 3;
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*p1 = half / 3;
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*p2 = 2;
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} else if (half % 7 == 0) {
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*p0 = 7;
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*p1 = half / 7;
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*p2 = 2;
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}
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} else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
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*p0 = 3;
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*p1 = 1;
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*p2 = p / 3;
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} else if (p == 5 || p == 7) {
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*p0 = p;
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*p1 = 1;
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*p2 = 1;
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} else if (p == 15) {
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*p0 = 3;
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*p1 = 1;
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*p2 = 5;
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} else if (p == 21) {
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*p0 = 7;
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*p1 = 1;
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*p2 = 3;
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} else if (p == 35) {
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*p0 = 7;
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*p1 = 1;
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*p2 = 5;
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}
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}
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static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
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{
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memset(ctx, 0, sizeof(*ctx));
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ctx->min_deviation = UINT64_MAX;
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}
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static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
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uint64 afe_clock,
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int ref_clock,
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uint64 central_freq,
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uint32 p0, uint32 p1, uint32 p2)
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{
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uint64 dco_freq;
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switch (central_freq) {
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case 9600000000ULL:
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params->central_freq = 0;
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break;
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case 9000000000ULL:
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params->central_freq = 1;
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break;
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case 8400000000ULL:
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params->central_freq = 3;
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}
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switch (p0) {
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case 1:
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params->pdiv = 0;
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break;
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case 2:
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params->pdiv = 1;
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break;
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case 3:
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params->pdiv = 2;
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break;
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case 7:
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params->pdiv = 4;
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break;
|
||||
default:
|
||||
TRACE("%s: Incorrect PDiv\n", __func__);
|
||||
}
|
||||
|
||||
switch (p2) {
|
||||
case 5:
|
||||
params->kdiv = 0;
|
||||
break;
|
||||
case 2:
|
||||
params->kdiv = 1;
|
||||
break;
|
||||
case 3:
|
||||
params->kdiv = 2;
|
||||
break;
|
||||
case 1:
|
||||
params->kdiv = 3;
|
||||
break;
|
||||
default:
|
||||
TRACE("%s: Incorrect KDiv\n", __func__);
|
||||
}
|
||||
|
||||
params->qdiv_ratio = p1;
|
||||
params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
|
||||
|
||||
dco_freq = p0 * p1 * p2 * afe_clock;
|
||||
|
||||
/*
|
||||
* Intermediate values are in Hz.
|
||||
* Divide by MHz to match bsepc
|
||||
*/
|
||||
params->dco_integer = (uint64)dco_freq / ((uint64)ref_clock * 1000);
|
||||
params->dco_fraction = (
|
||||
(uint64)dco_freq / ((uint64)ref_clock / 1000) -
|
||||
(uint64)params->dco_integer * 1000000 * 0x8000) /
|
||||
1000000;
|
||||
}
|
||||
|
||||
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
|
||||
|
||||
bool
|
||||
skl_ddi_calculate_wrpll(int clock /* in Hz */,
|
||||
int ref_clock,
|
||||
struct skl_wrpll_params *wrpll_params)
|
||||
{
|
||||
uint64 afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
|
||||
uint64 dco_central_freq[3] = { 8400000000ULL,
|
||||
9000000000ULL,
|
||||
9600000000ULL };
|
||||
static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
|
||||
24, 28, 30, 32, 36, 40, 42, 44,
|
||||
48, 52, 54, 56, 60, 64, 66, 68,
|
||||
70, 72, 76, 78, 80, 84, 88, 90,
|
||||
92, 96, 98 };
|
||||
static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
|
||||
static const struct {
|
||||
const int *list;
|
||||
unsigned int n_dividers;
|
||||
} dividers[] = {
|
||||
{ even_dividers, ARRAY_SIZE(even_dividers) },
|
||||
{ odd_dividers, ARRAY_SIZE(odd_dividers) },
|
||||
};
|
||||
struct skl_wrpll_context ctx;
|
||||
unsigned int dco, d, i;
|
||||
unsigned int p0, p1, p2;
|
||||
|
||||
skl_wrpll_context_init(&ctx);
|
||||
|
||||
for (d = 0; d < ARRAY_SIZE(dividers); d++) {
|
||||
for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
|
||||
for (i = 0; i < dividers[d].n_dividers; i++) {
|
||||
unsigned int p = dividers[d].list[i];
|
||||
uint64 dco_freq = p * afe_clock;
|
||||
|
||||
skl_wrpll_try_divider(&ctx,
|
||||
dco_central_freq[dco],
|
||||
dco_freq,
|
||||
p);
|
||||
/*
|
||||
* Skip the remaining dividers if we're sure to
|
||||
* have found the definitive divider, we can't
|
||||
* improve a 0 deviation.
|
||||
*/
|
||||
if (ctx.min_deviation == 0)
|
||||
goto skip_remaining_dividers;
|
||||
}
|
||||
}
|
||||
|
||||
skip_remaining_dividers:
|
||||
/*
|
||||
* If a solution is found with an even divider, prefer
|
||||
* this one.
|
||||
*/
|
||||
if (d == 0 && ctx.p)
|
||||
break;
|
||||
}
|
||||
|
||||
if (!ctx.p) {
|
||||
TRACE("%s: No valid divider found for %dHz\n", __func__, clock);
|
||||
return false;
|
||||
}
|
||||
|
||||
/*
|
||||
* gcc incorrectly analyses that these can be used without being
|
||||
* initialized. To be fair, it's hard to guess.
|
||||
*/
|
||||
p0 = p1 = p2 = 0;
|
||||
skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
|
||||
skl_wrpll_params_populate(wrpll_params, afe_clock, ref_clock,
|
||||
ctx.central_freq, p0, p1, p2);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
@ -31,6 +31,15 @@ struct pll_limits {
|
||||
uint32 max_vco;
|
||||
};
|
||||
|
||||
struct skl_wrpll_params {
|
||||
uint32 dco_fraction;
|
||||
uint32 dco_integer;
|
||||
uint32 qdiv_ratio;
|
||||
uint32 qdiv_mode;
|
||||
uint32 kdiv;
|
||||
uint32 pdiv;
|
||||
uint32 central_freq;
|
||||
};
|
||||
|
||||
bool valid_pll_divisors(pll_divisors* divisors, pll_limits* limits);
|
||||
void compute_pll_divisors(display_timing* current, pll_divisors* divisors,
|
||||
@ -38,5 +47,9 @@ void compute_pll_divisors(display_timing* current, pll_divisors* divisors,
|
||||
|
||||
void refclk_activate_ilk(bool hasPanel);
|
||||
|
||||
void hsw_ddi_calculate_wrpll(int clock /* in Hz */,
|
||||
unsigned *r2_out, unsigned *n2_out, unsigned *p_out);
|
||||
bool skl_ddi_calculate_wrpll(int clock /* in Hz */,
|
||||
int ref_clock, struct skl_wrpll_params *wrpll_params);
|
||||
|
||||
#endif /* INTEL_EXTREME_PLL_H */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user