* edid1_detailed_timing_raw was missing
a field which threw off the sync bits.
* The result was the monitor will receive
a different sync polarity than it requested.
Most monitors handle this, but it is still
a bug
* Remove non-generic radeon dp_get_lane_count
* Set lane count and link rate at set_display_mode
* Pass entire mode to pll_set vs only pixel clock for DP code
* Add helpers for DP config data to common code
* Obtain more correct link rate
* This puts the registers in a better state and ensures
all model dependant defines are prefixed with card series
* Consolidate evergreen defines into single header
* First steps at getting card command processor wired
up to the ring buffers.
* Code doesn't run yet as I have *no* idea what happens
when these rings are in an invalid state.
* General DisplayPort functions in common dp.cpp
* DP port information struct in common header
* Please don't use this private accelerant common DP
code just yet as it is very early.
* The AtomBIOS timeout fix has made my DP bridge
stop working
* The current DisplayPort code is a little lacking
on DP link training... I think thats the cause.
* This puts the first steps towards DP training
in place.
* I plan on trying to make some of this DP stuff
common accelerant stuff after it works.
* I'd rather this be common code, but I don't have access
to the DisplayPort specifications. If I added it as common
code I would want to be 100% it was complete and variables
were named properly.
* For now putting in radeon_hd private headers
* add temperature query support for Juniper, Sumo, Evergreen, and North Islands
* add missing thermal defines for evergreen cards
* northern island cards use the evergreen thermal calculations
* add a few missing/needed header defines
* show GPU temp in millidegrees C on r600/r700
* evergreen+ support soon
* function may be moved to driver long term once testing done
* add missing chipset ranges
* add a few more older (X1200) PCI ID's (mostly IGP)
* add code to detect and set frame buffer size on old chipsets
* we get to the connector detection currently and fail due to the
lack of legacy support on my X1200 IGP
* evergreen headers are split due to different
header copyrights
* detect and set up evergreen memory controler
* change the way we manage radeon chipsets to
more closely match drm driver as the chipset
model numbers aren't in order and change from
numbers to names.
* check for evergreen when populating frame buffer
information.
* style cleanup
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@43225 a95241bf-73f2-0310-859d-f6bbb57e9c96
There were a large number if incorrect, duplicated, misplaced
registers that were leading to bugs in the code. This is my first
shot at cleaning them up. Luckly as we are using AtomBIOS the number
of registers we need to know about is shrinking.
* remove registers left over from register banging days
* r770 is less then r710, r720 in the drm sources. Fix in code.
* enable newer radeons for testing
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42930 a95241bf-73f2-0310-859d-f6bbb57e9c96
* don't resize the frame buffer after mapping it.. doesn't make sense
* add memory controller code and program the memory controller for r600
* remove unneeded frame_buffer_int
* don't malloc mc_info, waste of time
* fix scaler setting
* vramStart in mc should be 0... get vertical colored lines however when this
this is set properly (everything in mc_info is the MC view of FB BAR)
When vramStart is the FB physical address... i get proper video on some cards
... thoughts?
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42924 a95241bf-73f2-0310-859d-f6bbb57e9c96
* we can now utilize these chipset
flags throughout the driver to better id
cards and features
* remove leftover BIOS size define from intel skel
* no *real* functional change
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42904 a95241bf-73f2-0310-859d-f6bbb57e9c96
* add potential support for IGP chipsets
* igp code is *untested* and should work *in theory*
* potentially resolves#8040 / #8046 ?
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42901 a95241bf-73f2-0310-859d-f6bbb57e9c96
* will fix other var names to match style guidelines
shortly
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42891 a95241bf-73f2-0310-859d-f6bbb57e9c96
base intel_extreme driver long ago
* no functional change
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42880 a95241bf-73f2-0310-859d-f6bbb57e9c96
* correct? color mode setting bug
* fix var naming to match style guidelines
* add a few missing register defines
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42879 a95241bf-73f2-0310-859d-f6bbb57e9c96
(they are actually reversed), so introduce a find_reg() inline function to map
such regs individually instead. Should fix interrupt storms on SandyBridge.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42870 a95241bf-73f2-0310-859d-f6bbb57e9c96
* Also add the definitions and some specifics for IronLake (ILK), but keep the
IDs disabled as at least the one version I can test with doesn't work yet.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42869 a95241bf-73f2-0310-859d-f6bbb57e9c96
* Make the pointer style consistent accross all components, which should make it
easier when working all over the place.
* 80 char limits.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42863 a95241bf-73f2-0310-859d-f6bbb57e9c96
control block. Doesn't matter on (G)MCH (they are the same register block tehre)
but fixes mode setting on PCH again.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42862 a95241bf-73f2-0310-859d-f6bbb57e9c96
register blocks and we encode their block into the register definition. On
register access these blocks are then translated into the final address.
* Set up the register blocks for (G)MCH and PCH variants.
* Remove most SandyBridge code that was actually PCH specific and is now taken
care of automatically.
* This will temporarily break SandyBridge support again until the right
transcoders are actually programmed.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42857 a95241bf-73f2-0310-859d-f6bbb57e9c96
(the one in my new ThinkPad X1). The PLL is still off a bit so it has a few
blurry stripes, but EDID and mode setting basically works.
* Starting with IronLake the north/south bridge or (G)MCH/ICH setup was moved
into a platform control hub (PCH) which means that many registers previously
located in the GMCH are now in the PCH and have a new address.
* I'm committing this mostly because this way the additions are more easy to
follow. It is a bit messy and I'll clean it up more and possibly make it a
bit more generic. Also most of these changes actually apply to IronLake and up
and aren't SandyBridge specific, so a few of those additions will still get a
broader scope and new chips will be added.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42839 a95241bf-73f2-0310-859d-f6bbb57e9c96
