Add first hints of thermal monitoring on radeon cards

* add a few missing/needed header defines
* show GPU temp in millidegrees C on r600/r700
* evergreen+ support soon
* function may be moved to driver long term once testing done
This commit is contained in:
Alexander von Gluck IV 2011-11-21 17:54:27 -06:00
parent 97b846e874
commit 0cd972316d
5 changed files with 64 additions and 14 deletions

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@ -183,4 +183,10 @@
#define R600_HDMI_CONFIG1 0x7600
#define R600_HDMI_CONFIG2 0x7a00
/* Thermal information */
#define R600_CG_THERMAL_STATUS 0x7F4
#define R600_ASIC_T(x) ((x) << 0)
#define R600_ASIC_T_MASK 0x1FF
#define R600_ASIC_T_SHIFT 0
#endif

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@ -121,25 +121,25 @@
#define CMDFIFO_AVAIL_MASK 0x0000000F
#define GUI_ACTIVE (1<<31)
#define GRBM_STATUS2 0x8014
#define CG_MULT_THERMAL_STATUS 0x740
#define ASIC_T(x) ((x) << 16)
#define ASIC_T_MASK 0x3FF0000
#define ASIC_T_SHIFT 16
#endif
#define HDP_HOST_PATH_CNTL 0x2C00
#define HDP_NONSURFACE_BASE 0x2C04
#define HDP_NONSURFACE_INFO 0x2C08
#define HDP_NONSURFACE_SIZE 0x2C0C
#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
#define HDP_TILING_CONFIG 0x2F3C
#define HDP_DEBUG1 0x2F34
#define R700_CG_MULT_THERMAL_STATUS 0x740
#define R700_ASIC_T(x) ((x) << 16)
#define R700_ASIC_T_MASK 0x3FF0000
#define R700_ASIC_T_SHIFT 16
#define R700_MC_SHARED_CHMAP 0x2004
#define HDP_HOST_PATH_CNTL 0x2C00
#define HDP_NONSURFACE_BASE 0x2C04
#define HDP_NONSURFACE_INFO 0x2C08
#define HDP_NONSURFACE_SIZE 0x2C0C
#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
#define HDP_TILING_CONFIG 0x2F3C
#define HDP_DEBUG1 0x2F34
#define R700_MC_SHARED_CHMAP 0x2004
#define NOOFCHAN_SHIFT 12
#define NOOFCHAN_MASK 0x00003000
#define R700_MC_SHARED_CHREMAP 0x2008
#define R700_MC_SHARED_CHREMAP 0x2008
#define R700_MC_ARB_RAMCFG 0x2760
#define NOOFBANK_SHIFT 0

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@ -287,6 +287,9 @@ radeon_init_accelerant(int device)
radeon_gpu_mc_setup();
TRACE("%s: Current GPU temperature: %" B_PRId32 " mC\n",
__func__, radeon_get_temp());
TRACE("%s done\n", __func__);
return B_OK;
}

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@ -774,3 +774,43 @@ radeon_gpu_gpio_setup()
return B_OK;
}
int32
radeon_get_temp()
{
// return GPU temp in millidegrees C
radeon_shared_info &info = *gInfo->shared_info;
uint32 rawTemp = 0; // temp
int32 finalTemp = 0; // actual_temp
if (info.chipsetID >= RADEON_RV770) {
rawTemp = (Read32(OUT, R700_CG_MULT_THERMAL_STATUS) & R700_ASIC_T_MASK)
>> R700_ASIC_T_SHIFT;
if (rawTemp & 0x400)
finalTemp = -256;
else if (rawTemp & 0x200)
finalTemp = 255;
else if (rawTemp & 0x100) {
finalTemp = rawTemp & 0x1ff;
finalTemp |= ~0x1ff;
} else
finalTemp = rawTemp & 0xff;
return (finalTemp * 1000) / 2;
} else if (info.chipsetID >= RADEON_R600) {
rawTemp = (Read32(OUT, R600_CG_THERMAL_STATUS) & R600_ASIC_T_MASK)
>> R600_ASIC_T_SHIFT;
finalTemp = rawTemp & 0xff;
if (rawTemp & 0x100)
finalTemp -= 256;
return finalTemp * 1000;
}
return -1;
}

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@ -177,6 +177,7 @@ status_t radeon_gpu_irq_setup();
status_t radeon_gpu_gpio_setup();
status_t radeon_gpu_i2c_attach(uint32 id, uint8 hw_line);
bool radeon_gpu_read_edid(uint32 connector, edid1_info *edid);
int32 radeon_get_temp();
#endif