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intel_810: Style cleanup. No functional change

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* I think the FunctionNames need to change to function_name
This commit is contained in:
Alexander von Gluck IV 2012-05-30 16:09:52 -05:00
parent e0ee3b7971
commit 0e8316cc90
11 changed files with 97 additions and 102 deletions
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14
headers/private/graphics/intel_810/DriverInterface.h
View File

@ -5,7 +5,6 @@
* Authors:
* Gerald Zajac
*/
#ifndef DRIVERINTERFACE_H
#define DRIVERINTERFACE_H
@ -23,7 +22,6 @@
#define ENABLE_DEBUG_TRACE // if defined, turns on debug output to syslog
#define ARRAY_SIZE(a) (int(sizeof(a) / sizeof(a[0]))) // get number of elements in an array
@ -81,12 +79,12 @@ struct SharedInfo {
bool bAccelerantInUse; // true = accelerant has been initialized
// Memory mappings.
area_id regsArea; // area_id for the memory mapped registers. It will
// be cloned into accelerant's address space.
area_id videoMemArea; // video memory area_id. Addr's shared with all teams.
area_id regsArea; // area_id for the memory mapped registers. It
// will be cloned into accelerant address space.
area_id videoMemArea; // addr shared with all teams.
addr_t videoMemAddr; // virtual video memory addr
phys_addr_t videoMemPCI; // physical video memory addr
uint32 videoMemSize; // video memory size in bytes (for frame buffer).
uint32 videoMemSize; // video memory size in bytes (for frame buffer)
uint32 maxFrameBufferSize; // max available video memory for frame buffer
@ -95,7 +93,7 @@ struct SharedInfo {
uint32 colorSpaceCount; // number of color spaces in array colorSpaces
// List of screen modes.
area_id modeArea; // area containing list of display modes the driver supports
area_id modeArea; // area containing list of display modes
uint32 modeCount; // number of display modes in the list
DisplayModeEx displayMode; // current display mode configuration
@ -103,7 +101,7 @@ struct SharedInfo {
edid1_info edidInfo;
bool bHaveEDID; // true = EDID info from device is in edidInfo
Benaphore engineLock; // for serializing access to the acceleration engine
Benaphore engineLock; // serializing access to the acceleration engine
};

13
src/add-ons/accelerants/intel_810/accelerant.cpp
View File

@ -6,6 +6,7 @@
* Gerald Zajac
*/
#include "accelerant.h"
#include <errno.h>
@ -13,7 +14,6 @@
#include <unistd.h>
AccelerantInfo gInfo; // global data used by source files of accelerant
static uint32 videoValue;
@ -32,7 +32,7 @@ SuppressArtifacts(void* dataPtr)
// the video memory. This is because some artifacts still occur at the
// top of the screen if the accessed memory is at the beginning of the
// video memory.
// Note that this function will reduce the general performance of a
// computer somewhat, but it is much less of a hit than if double
// buffering was used for the video. Base on the frame rate of the
@ -40,8 +40,7 @@ SuppressArtifacts(void* dataPtr)
SharedInfo& si = *((SharedInfo*)dataPtr);
while (true)
{
while (true) {
uint32* src = ((uint32*)(si.videoMemAddr)) + si.videoMemSize / 4 - 1;
uint32 count = 65000;
@ -74,13 +73,13 @@ InitCommon(int fileDesc)
(void**)&(gInfo.sharedInfo), B_ANY_ADDRESS, B_READ_AREA | B_WRITE_AREA,
sharedArea);
if (gInfo.sharedInfoArea < 0)
return gInfo.sharedInfoArea; // sharedInfoArea has error code
return gInfo.sharedInfoArea; // sharedInfoArea has error code
gInfo.regsArea = clone_area("i810 regs area", (void**)&(gInfo.regs),
B_ANY_ADDRESS, B_READ_AREA | B_WRITE_AREA, gInfo.sharedInfo->regsArea);
if (gInfo.regsArea < 0) {
delete_area(gInfo.sharedInfoArea);
return gInfo.regsArea; // regsArea has error code
return gInfo.regsArea; // regsArea has error code
}
return B_OK;
@ -129,7 +128,7 @@ InitAccelerant(int fileDesc)
// Ensure that this function won't be executed again
// (copies should be clones)
si.bAccelerantInUse = true;
thread_id threadID = spawn_thread(SuppressArtifacts,
"SuppressArtifacts_Thread", B_DISPLAY_PRIORITY,
gInfo.sharedInfo);

10
src/add-ons/accelerants/intel_810/accelerant.h
View File

@ -5,12 +5,11 @@
* Authors:
* Gerald Zajac
*/
#ifndef _ACCELERANT_H
#define _ACCELERANT_H
#include "DriverInterface.h"
#include "DriverInterface.h"
#undef TRACE
@ -24,7 +23,6 @@ extern "C" void _sPrintf(const char* format, ...);
// Global data used by various source files of the accelerant.
struct AccelerantInfo {
int deviceFileDesc; // file descriptor of kernel driver
@ -48,7 +46,7 @@ extern AccelerantInfo gInfo;
// the functions that are unique to a particular chip family, will be prefixed
// with the name of the family, and the functions that are applicable to all
// chips will have no prefix.
//================================================================
// ================================================================
#if defined(__cplusplus)
extern "C" {
@ -95,11 +93,9 @@ status_t SyncToToken(sync_token* st);
#endif
// Prototypes for other functions that are called from source files other than
// where they are defined.
//============================================================================
// ============================================================================
status_t CreateModeList(bool (*checkMode)(const display_mode* mode));
bool IsModeUsable(const display_mode* mode);

11
src/add-ons/accelerants/intel_810/engine.cpp
View File

@ -6,6 +6,7 @@
* Gerald Zajac
*/
#include "accelerant.h"
#include "i810_regs.h"
@ -22,7 +23,7 @@ AccelerantEngineCount(void)
status_t
AcquireEngine(uint32 capabilities, uint32 maxWait,
sync_token* syncToken, engine_token** engineToken)
sync_token* syncToken, engine_token** engineToken)
{
(void)capabilities; // avoid compiler warning for unused arg
(void)maxWait; // avoid compiler warning for unused arg
@ -55,9 +56,9 @@ WaitEngineIdle(void)
// Wait until engine is idle.
int k = 10000000;
while ((INREG16(INST_DONE) & 0x7B) != 0x7B && k > 0)
k--;
k--;
}
@ -73,9 +74,9 @@ GetSyncToken(engine_token* engineToken, sync_token* syncToken)
status_t
SyncToToken(sync_token* syncToken)
{
(void)syncToken; // avoid compiler warning for unused arg
(void)syncToken;
// avoid compiler warning for unused arg
WaitEngineIdle();
return B_OK;
}

4
src/add-ons/accelerants/intel_810/hooks.cpp
View File

@ -6,13 +6,15 @@
* Gerald Zajac
*/
#include "accelerant.h"
extern "C" void*
get_accelerant_hook(uint32 feature, void* data)
{
(void)data; // avoid compiler warning for unused arg
(void)data;
// avoid compiler warning for unused arg
switch (feature) {
// General

3
src/add-ons/accelerants/intel_810/i810_init.cpp
View File

@ -19,10 +19,9 @@
#include "i810_regs.h"
bool
I810_GetColorSpaceParams(int colorSpace, uint8& bitsPerPixel,
uint32& maxPixelClock)
uint32& maxPixelClock)
{
// Get parameters for a color space which is supported by the i810 chips.
// Argument maxPixelClock is in KHz.

30
src/add-ons/accelerants/intel_810/i810_mode.cpp
View File

@ -14,6 +14,7 @@
All Rights Reserved.
*/
#include "accelerant.h"
#include "i810_regs.h"
@ -22,15 +23,14 @@
#include <unistd.h>
// I810_CalcVCLK -- Determine closest clock frequency to the one requested.
#define MAX_VCO_FREQ 600.0
#define TARGET_MAX_N 30
#define REF_FREQ 24.0
#define CALC_VCLK(m,n,p) (double)m / ((double)n * (1 << p)) * 4 * REF_FREQ
static void
CalcVCLK(double freq, uint16& clkM, uint16& clkN, uint16& clkP) {
int m, n, p;
@ -65,8 +65,8 @@ CalcVCLK(double freq, uint16& clkM, uint16& clkN, uint16& clkP) {
f_best = f_out;
errBest = f_err;
}
} while ((fabs(f_err) >= errTarget) &&
((n <= TARGET_MAX_N) || (fabs(errBest) > errMax)));
} while ((fabs(f_err) >= errTarget) && ((n <= TARGET_MAX_N)
|| (fabs(errBest) > errMax)));
if (fabs(f_err) < errTarget) {
m_best = m;
@ -83,7 +83,7 @@ CalcVCLK(double freq, uint16& clkM, uint16& clkN, uint16& clkP) {
}
static void
static void
SetCrtcTimingValues(const DisplayModeEx& mode)
{
// Set the timing values for CRTC registers cr00 to cr18, and some extended
@ -104,7 +104,7 @@ SetCrtcTimingValues(const DisplayModeEx& mode)
int vBlank_e = vTotal; // end of vertical blanking
uint16 offset = mode.bytesPerRow / 8;
// CRTC Controller values
uint8 crtc[25];
@ -151,7 +151,7 @@ SetCrtcTimingValues(const DisplayModeEx& mode)
WriteCrtcReg(j, crtc[j]);
// Set the extended CRTC reg's.
WriteCrtcReg(EXT_VERT_TOTAL, vTotal >> 8);
WriteCrtcReg(EXT_VERT_DISPLAY, vDisp_e >> 8);
WriteCrtcReg(EXT_VERT_SYNC_START, vSync_s >> 8);
@ -161,7 +161,7 @@ SetCrtcTimingValues(const DisplayModeEx& mode)
WriteCrtcReg(EXT_OFFSET, offset >> 8);
WriteCrtcReg(INTERLACE_CNTL, INTERLACE_DISABLE); // turn off interlace
// Enable high resolution mode.
WriteCrtcReg(IO_CTNL, ReadCrtcReg(IO_CTNL) | EXTENDED_CRTC_CNTL);
}
@ -211,7 +211,7 @@ I810_SetDisplayMode(const DisplayModeEx& mode)
// Set the address mapping to use the frame buffer memory mapped via the
// GTT table instead of the VGA buffer.
uint8 addrMapping = ReadGraphReg(ADDRESS_MAPPING);
addrMapping &= 0xE0; // preserve reserved bits 7:5
addrMapping |= (GTT_MEM_MAP_ENABLE | LINEAR_MODE_ENABLE);
@ -224,7 +224,7 @@ I810_SetDisplayMode(const DisplayModeEx& mode)
temp = INREG8(BITBLT_CNTL) & ~COLEXP_MODE;
temp |= (mode.bitsPerPixel == 8 ? COLEXP_8BPP : COLEXP_16BPP);
OUTREG8(BITBLT_CNTL, temp);
// Turn on 8 bit dac mode so that the indexed colors are displayed properly,
// and put display in high resolution mode.
@ -236,15 +236,15 @@ I810_SetDisplayMode(const DisplayModeEx& mode)
OUTREG16(EIR, 0);
temp32 = INREG32(FWATER_BLC);
temp32 &= ~(LM_BURST_LENGTH | LM_FIFO_WATERMARK |
MM_BURST_LENGTH | MM_FIFO_WATERMARK);
temp32 &= ~(LM_BURST_LENGTH | LM_FIFO_WATERMARK
| MM_BURST_LENGTH | MM_FIFO_WATERMARK);
temp32 |= I810_GetWatermark(mode);
OUTREG32(FWATER_BLC, temp32);
// Enable high resolution mode.
WriteCrtcReg(IO_CTNL, ReadCrtcReg(IO_CTNL) | EXTENDED_CRTC_CNTL);
I810_AdjustFrame(mode);
I810_AdjustFrame(mode);
return B_OK;
}
@ -255,13 +255,13 @@ I810_AdjustFrame(const DisplayModeEx& mode)
// Adjust start address in frame buffer.
uint32 address = ((mode.v_display_start * mode.virtual_width
+ mode.h_display_start) * mode.bytesPerPixel) >> 2;
+ mode.h_display_start) * mode.bytesPerPixel) >> 2;
WriteCrtcReg(START_ADDR_LO, address & 0xff);
WriteCrtcReg(START_ADDR_HI, (address >> 8) & 0xff);
WriteCrtcReg(EXT_START_ADDR_HI, (address >> 22) & 0xff);
WriteCrtcReg(EXT_START_ADDR,
((address >> 16) & 0x3f) | EXT_START_ADDR_ENABLE);
((address >> 16) & 0x3f) | EXT_START_ADDR_ENABLE);
}

26
src/add-ons/accelerants/intel_810/i810_regs.h
View File

@ -13,7 +13,6 @@
Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
All Rights Reserved.
*/
#ifndef __I810_REGS_H__
#define __I810_REGS_H__
@ -29,7 +28,7 @@
#define EXT_HORIZ_TOTAL 0x35
#define EXT_HORIZ_BLANK 0x39
#define EXT_START_ADDR 0x40
#define EXT_START_ADDR_ENABLE 0x80
#define EXT_START_ADDR_ENABLE 0x80
#define EXT_OFFSET 0x41
#define EXT_START_ADDR_HI 0x42
#define INTERLACE_CNTL 0x70
@ -123,37 +122,48 @@
(OUTREG(addr, (INREG(addr) & ~mask) | (value & mask)))
static inline uint8 ReadCrtcReg(uint8 index)
static inline uint8
ReadCrtcReg(uint8 index)
{
OUTREG8(CRTC_INDEX, index);
return INREG8(CRTC_DATA);
}
static inline void WriteCrtcReg(uint8 index, uint8 value)
static inline void
WriteCrtcReg(uint8 index, uint8 value)
{
OUTREG8(CRTC_INDEX, index);
OUTREG8(CRTC_DATA, value);
}
static inline uint8 ReadGraphReg(uint8 index)
static inline uint8
ReadGraphReg(uint8 index)
{
OUTREG8(GRAPH_INDEX, index);
return INREG8(GRAPH_DATA);
}
static inline void WriteGraphReg(uint8 index, uint8 value)
static inline void
WriteGraphReg(uint8 index, uint8 value)
{
OUTREG8(GRAPH_INDEX, index);
OUTREG8(GRAPH_DATA, value);
}
static inline uint8 ReadSeqReg(uint8 index)
static inline uint8
ReadSeqReg(uint8 index)
{
OUTREG8(SEQ_INDEX, index);
return INREG8(SEQ_DATA);
}
static inline void WriteSeqReg(uint8 index, uint8 value)
static inline void
WriteSeqReg(uint8 index, uint8 value)
{
OUTREG8(SEQ_INDEX, index);
OUTREG8(SEQ_DATA, value);

22
src/add-ons/accelerants/intel_810/i810_watermark.cpp
View File

@ -34,6 +34,7 @@ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
#include "accelerant.h"
@ -104,7 +105,6 @@ static WatermarkInfo watermarks_16[] = {
};
uint32
I810_GetWatermark(const DisplayModeEx& mode)
{
@ -115,16 +115,16 @@ I810_GetWatermark(const DisplayModeEx& mode)
// pixel clock.
switch (mode.bitsPerPixel) {
case 8:
table = watermarks_8;
tableLen = ARRAY_SIZE(watermarks_8);
break;
case 16:
table = watermarks_16;
tableLen = ARRAY_SIZE(watermarks_16);
break;
default:
return 0;
case 8:
table = watermarks_8;
tableLen = ARRAY_SIZE(watermarks_8);
break;
case 16:
table = watermarks_16;
tableLen = ARRAY_SIZE(watermarks_16);
break;
default:
return 0;
}
uint32 i;

18
src/add-ons/accelerants/intel_810/mode.cpp
View File

@ -1,11 +1,12 @@
/*
* Copyright 2007-2012 Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT license.
*
* Authors:
* Gerald Zajac
*/
#include "accelerant.h"
#include <create_display_modes.h> // common accelerant header file
@ -13,7 +14,6 @@
#include <unistd.h>
static bool
IsThereEnoughFBMemory(const display_mode* mode, uint32 bitsPerPixel)
{
@ -31,11 +31,10 @@ IsThereEnoughFBMemory(const display_mode* mode, uint32 bitsPerPixel)
uint32 bytesPerPixel = (bitsPerPixel + 7) / 8;
return (maxWidth * maxHeight * bytesPerPixel
<= gInfo.sharedInfo->maxFrameBufferSize);
<= gInfo.sharedInfo->maxFrameBufferSize);
}
bool
IsModeUsable(const display_mode* mode)
{
@ -101,7 +100,7 @@ CreateModeList(bool (*checkMode)(const display_mode* mode))
TRACE("CreateModeList(); EDID version %d.%d out of range\n",
rawEdid.version.version, rawEdid.version.revision);
} else {
edid_decode(&si.edidInfo, &rawEdid); // decode & save EDID info
edid_decode(&si.edidInfo, &rawEdid); // decode & save EDID info
si.bHaveEDID = true;
}
}
@ -134,7 +133,6 @@ CreateModeList(bool (*checkMode)(const display_mode* mode))
}
status_t
ProposeDisplayMode(display_mode* target, const display_mode* low,
const display_mode* high)
@ -223,7 +221,6 @@ SetDisplayMode(display_mode* pMode)
}
status_t
MoveDisplay(uint16 horizontalStart, uint16 verticalStart)
{
@ -269,7 +266,7 @@ GetModeList(display_mode* dmList)
status_t
GetDisplayMode(display_mode* current_mode)
{
*current_mode = gInfo.sharedInfo->displayMode; // return current display mode
*current_mode = gInfo.sharedInfo->displayMode; // current display mode
return B_OK;
}
@ -281,7 +278,7 @@ GetFrameBufferConfig(frame_buffer_config* pFBC)
pFBC->frame_buffer = (void*)((addr_t)(si.videoMemAddr));
pFBC->frame_buffer_dma = (void*)((addr_t)(si.videoMemPCI));
pFBC->bytes_per_row = si.displayMode.virtual_width
pFBC->bytes_per_row = si.displayMode.virtual_width
* si.displayMode.bytesPerPixel;
return B_OK;
@ -317,9 +314,7 @@ GetPixelClockLimits(display_mode* mode, uint32* low, uint32* high)
}
#ifdef __HAIKU__
status_t
GetEdidInfo(void* info, size_t size, uint32* _version)
{
@ -335,5 +330,4 @@ GetEdidInfo(void* info, size_t size, uint32* _version)
*_version = EDID_VERSION_1;
return B_OK;
}
#endif // __HAIKU__

48
src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp
View File

@ -6,6 +6,7 @@
* Gerald Zajac
*/
#include <AGP.h>
#include <KernelExport.h>
#include <PCI.h>
@ -47,18 +48,18 @@ struct ChipInfo {
// This table maps a PCI device ID to a chip type identifier and the chip name.
static const ChipInfo chipTable[] = {
{ 0x7121, "i810" },
{ 0x7123, "i810-dc100" },
{ 0x7125, "i810e" },
{ 0x1132, "i815" },
{ 0, NULL }
{ 0x7121, "i810" },
{ 0x7123, "i810-dc100" },
{ 0x7125, "i810e" },
{ 0x1132, "i815" },
{ 0, NULL }
};
struct DeviceInfo {
uint32 openCount; // count of how many times device has been opened
uint32 openCount; // how many times device has been opened
int32 flags;
area_id sharedArea; // area shared between driver and accelerants
area_id sharedArea; // shared between driver and accelerants
SharedInfo* sharedInfo; // pointer to shared info area memory
vuint8* regs; // pointer to memory mapped registers
const ChipInfo* pChipInfo; // info about the selected chip
@ -76,13 +77,12 @@ static pci_module_info* gPCI;
// Prototypes for device hook functions.
static status_t device_open(const char* name, uint32 flags, void** cookie);
static status_t device_close(void* dev);
static status_t device_free(void* dev);
static status_t device_read(void* dev, off_t pos, void* buf, size_t* len);
static status_t device_write(void* dev, off_t pos, const void* buf,
size_t* len);
size_t* len);
static status_t device_ioctl(void* dev, uint32 msg, void* buf, size_t len);
static device_hooks gDeviceHooks =
@ -100,9 +100,8 @@ static device_hooks gDeviceHooks =
};
// Video chip register definitions.
//=================================
// =================================
#define INTERRUPT_ENABLED 0x020a0
#define INTERRUPT_MASK 0x020a8
@ -116,7 +115,7 @@ static device_hooks gDeviceHooks =
// Macros for memory mapped I/O.
//==============================
// ==============================
#define INREG16(addr) (*((vuint16*)(di.regs + (addr))))
#define INREG32(addr) (*((vuint32*)(di.regs + (addr))))
@ -125,7 +124,6 @@ static device_hooks gDeviceHooks =
#define OUTREG32(addr, val) (*((vuint32*)(di.regs + (addr))) = (val))
static inline uint32
GetPCI(pci_info& info, uint8 offset, uint8 size)
{
@ -147,8 +145,8 @@ GetEdidFromBIOS(edid1_raw& edidRaw)
{
// Get the EDID info from the video BIOS, and return B_OK if successful.
#define ADDRESS_SEGMENT(address) ((addr_t)(address) >> 4)
#define ADDRESS_OFFSET(address) ((addr_t)(address) & 0xf)
#define ADDRESS_SEGMENT(address) ((addr_t)(address) >> 4)
#define ADDRESS_OFFSET(address) ((addr_t)(address) & 0xf)
vm86_state vmState;
@ -295,12 +293,12 @@ InitDevice(DeviceInfo& di)
if (di.gttArea < B_OK) {
TRACE("Unable to create GTT, error: 0x%lx\n", di.gttArea);
return B_NO_MEMORY;
}
}
memset((void*)(di.gttAddr), 0, gttSize);
// Get the physical address of the GTT, and set GTT address in the chip.
physical_entry entry;
status_t status = get_memory_map((void *)(di.gttAddr),
B_PAGE_SIZE, &entry, 1);
@ -309,8 +307,8 @@ InitDevice(DeviceInfo& di)
return status;
}
OUTREG32(PAGE_TABLE_CONTROL, entry.address | PAGE_TABLE_ENABLED);
INREG32(PAGE_TABLE_CONTROL);
OUTREG32(PAGE_TABLE_CONTROL, entry.address | PAGE_TABLE_ENABLED);
INREG32(PAGE_TABLE_CONTROL);
// Allocate video memory to be used for the frame buffer.
@ -395,7 +393,7 @@ GetNextSupportedDevice(uint32& pciIndex, pci_info& pciInfo)
while (pDevice->chipID != 0) { // end of table?
if (pDevice->chipID == pciInfo.device_id)
return pDevice; // matching device/chip found
return pDevice; // matching device/chip found
pDevice++;
}
@ -404,11 +402,10 @@ GetNextSupportedDevice(uint32& pciIndex, pci_info& pciInfo)
pciIndex++;
}
return NULL; // no supported device found
return NULL; // no supported device found
}
// #pragma mark - Kernel Interface
@ -471,8 +468,8 @@ init_driver(void)
// Compose device name.
sprintf(di.name, "graphics/" DEVICE_FORMAT,
di.pciInfo.vendor_id, di.pciInfo.device_id,
di.pciInfo.bus, di.pciInfo.device, di.pciInfo.function);
di.pciInfo.vendor_id, di.pciInfo.device_id,
di.pciInfo.bus, di.pciInfo.device, di.pciInfo.function);
TRACE("init_driver() match found; name: %s\n", di.name);
gDeviceNames[count] = di.name;
@ -526,7 +523,6 @@ find_device(const char* name)
}
// #pragma mark - Device Hooks
@ -555,7 +551,7 @@ device_open(const char* name, uint32 /*flags*/, void** cookie)
if (status < B_OK)
DeleteAreas(di); // error occurred; delete any areas created
}
gLock.Release();
if (status == B_OK) {