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* remove un-used registers that were left over from

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base intel_extreme driver long ago
* no functional change


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42880 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Alexander von Gluck IV 2011-10-18 18:11:26 +00:00
parent afbd52f16a
commit 9774c58f55
1 changed files with 0 additions and 79 deletions
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79
headers/private/graphics/radeon_hd/radeon_hd.h
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@ -196,85 +196,6 @@ struct radeon_free_graphics_memory {
#define VGA_RENDER_CONTROL 0x0300
#define VGA_VSTATUS_CNTL_MASK 0x00030000
// cursor
#define RADEON_CURSOR_CONTROL 0x70080
#define RADEON_CURSOR_BASE 0x70084
#define RADEON_CURSOR_POSITION 0x70088
#define RADEON_CURSOR_PALETTE 0x70090 // (- 0x7009f)
#define RADEON_CURSOR_SIZE 0x700a0
#define CURSOR_ENABLED (1UL << 31)
#define CURSOR_FORMAT_2_COLORS (0UL << 24)
#define CURSOR_FORMAT_3_COLORS (1UL << 24)
#define CURSOR_FORMAT_4_COLORS (2UL << 24)
#define CURSOR_FORMAT_ARGB (4UL << 24)
#define CURSOR_FORMAT_XRGB (5UL << 24)
#define CURSOR_POSITION_NEGATIVE 0x8000
#define CURSOR_POSITION_MASK 0x3fff
// overlay flip
#define COMMAND_OVERLAY_FLIP (0x11 << 23)
#define COMMAND_OVERLAY_CONTINUE (0 << 21)
#define COMMAND_OVERLAY_ON (1 << 21)
#define COMMAND_OVERLAY_OFF (2 << 21)
#define OVERLAY_UPDATE_COEFFICIENTS 0x1
// 2D acceleration
#define XY_COMMAND_SOURCE_BLIT 0x54c00006
#define XY_COMMAND_COLOR_BLIT 0x54000004
#define XY_COMMAND_SETUP_MONO_PATTERN 0x44400007
#define XY_COMMAND_SCANLINE_BLIT 0x49400001
#define COMMAND_COLOR_BLIT 0x50000003
#define COMMAND_BLIT_RGBA 0x00300000
#define COMMAND_MODE_SOLID_PATTERN 0x80
#define COMMAND_MODE_CMAP8 0x00
#define COMMAND_MODE_RGB15 0x02
#define COMMAND_MODE_RGB16 0x01
#define COMMAND_MODE_RGB32 0x03
// display
#define DISPLAY_CONTROL_ENABLED (1UL << 31)
#define DISPLAY_CONTROL_GAMMA (1UL << 30)
#define DISPLAY_CONTROL_COLOR_MASK (0x0fUL << 26)
#define DISPLAY_CONTROL_CMAP8 (2UL << 26)
#define DISPLAY_CONTROL_RGB15 (4UL << 26)
#define DISPLAY_CONTROL_RGB16 (5UL << 26)
#define DISPLAY_CONTROL_RGB32 (6UL << 26)
/* VIP bus */
#define RADEON_VIPH_CH0_DATA 0x0c00
#define RADEON_VIPH_CH1_DATA 0x0c04
#define RADEON_VIPH_CH2_DATA 0x0c08
#define RADEON_VIPH_CH3_DATA 0x0c0c
#define RADEON_VIPH_CH0_ADDR 0x0c10
#define RADEON_VIPH_CH1_ADDR 0x0c14
#define RADEON_VIPH_CH2_ADDR 0x0c18
#define RADEON_VIPH_CH3_ADDR 0x0c1c
#define RADEON_VIPH_CH0_SBCNT 0x0c20
#define RADEON_VIPH_CH1_SBCNT 0x0c24
#define RADEON_VIPH_CH2_SBCNT 0x0c28
#define RADEON_VIPH_CH3_SBCNT 0x0c2c
#define RADEON_VIPH_CH0_ABCNT 0x0c30
#define RADEON_VIPH_CH1_ABCNT 0x0c34
#define RADEON_VIPH_CH2_ABCNT 0x0c38
#define RADEON_VIPH_CH3_ABCNT 0x0c3c
#define RADEON_VIPH_CONTROL 0x0c40
# define RADEON_VIP_BUSY 0
# define RADEON_VIP_IDLE 1
# define RADEON_VIP_RESET 2
# define RADEON_VIPH_EN (1 << 21)
#define RADEON_VIPH_DV_LAT 0x0c44
#define RADEON_VIPH_BM_CHUNK 0x0c48
#define RADEON_VIPH_DV_INT 0x0c4c
#define RADEON_VIPH_TIMEOUT_STAT 0x0c50
#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010
#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010
#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000
#define RADEON_VIPH_REG_DATA 0x0084
#define RADEON_VIPH_REG_ADDR 0x0080
// PCI bridge memory management
// overlay