radeon_hd: Start work on proper DP link training
* The AtomBIOS timeout fix has made my DP bridge stop working * The current DisplayPort code is a little lacking on DP link training... I think thats the cause. * This puts the first steps towards DP training in place. * I plan on trying to make some of this DP stuff common accelerant stuff after it works.
This commit is contained in:
Alexander von Gluck IV
parent
6f7c0aadbe
commit
83e3a8ea50
@ -136,6 +136,7 @@
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#define DP_INTERLANE_ALIGN_DONE (1 << 0)
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#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
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#define DP_LINK_STATUS_UPDATED (1 << 7)
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#define DP_LINK_STATUS_SIZE 6
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#define DP_SINK_STATUS 0x205
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@ -14,6 +14,7 @@
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#include <edid.h>
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#include "atom.h"
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#include "displayport_reg.h"
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#include "encoder.h"
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#include "mode.h"
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#include "pll.h"
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@ -126,11 +127,22 @@ typedef struct {
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typedef struct {
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bool valid;
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uint32 connectorIndex;
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uint32 auxPin; // normally GPIO pin on GPU
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uint8 config[8]; // DP configuration data
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uint8 sinkType;
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uint8 clock;
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int laneCount;
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bool trainingUseEncoder;
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uint8 trainingAttempts;
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uint8 trainingSet[4];
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int trainingReadInterval;
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uint8 linkStatus[DP_LINK_STATUS_SIZE];
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bool eDPOn;
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} dp_info;
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@ -11,7 +11,6 @@
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#include <Debug.h>
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#include "accelerant.h"
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#include "accelerant_protos.h"
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#include "connector.h"
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#include "mode.h"
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@ -403,12 +402,15 @@ dp_setup_connectors()
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}
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uint32 gpioID = gConnector[index]->gpioID;
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uint32 hwPin = gGPIOInfo[gpioID]->hwPin;
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uint32 auxPin = gGPIOInfo[gpioID]->hwPin;
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gDPInfo[index]->auxPin = auxPin;
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gDPInfo[index]->connectorIndex = index;
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uint8 auxMessage[25];
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int result;
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result = dp_aux_read(hwPin, DP_DPCD_REV, auxMessage, 8, 0);
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result = dp_aux_read(auxPin, DP_DPCD_REV, auxMessage, 8, 0);
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if (result > 0) {
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gDPInfo[index]->valid = true;
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memcpy(gDPInfo[index]->config, auxMessage, 8);
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@ -419,14 +421,255 @@ dp_setup_connectors()
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}
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static bool
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dp_get_link_status(dp_info* dp)
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{
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int result = dp_aux_read(dp->auxPin, DP_LANE0_1_STATUS,
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dp->linkStatus, DP_LINK_STATUS_SIZE, 100);
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if (result <= 0) {
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ERROR("%s: DisplayPort link status failed\n", __func__);
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return false;
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}
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return true;
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}
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static uint8
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dp_get_lane_status(dp_info* dp, int lane)
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{
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int i = DP_LANE0_1_STATUS + (lane >> 1);
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int s = (lane & 1) * 4;
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uint8 l = dp->linkStatus[i - DP_LANE0_1_STATUS];
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return (l >> s) & 0xf;
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}
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static bool
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dp_clock_recovery_ok(dp_info* dp)
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{
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int lane;
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uint8 laneStatus;
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for (lane = 0; lane < dp->laneCount; lane++) {
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laneStatus = dp_get_lane_status(dp, lane);
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if ((laneStatus & DP_LANE_CR_DONE) == 0)
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return false;
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}
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return true;
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}
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static void
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dp_update_vs_emph(dp_info* dp)
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{
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// Set initial vs and emph on source
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transmitter_dig_setup(dp->connectorIndex, dp->clock, 0, dp->trainingSet[0],
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ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH);
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// Set vs and emph on the sink
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dp_aux_write(dp->auxPin, DP_TRAINING_LANE0_SET,
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dp->trainingSet, dp->laneCount, 0);
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}
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static uint8
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dp_get_adjust_request_voltage(dp_info* dp, int lane)
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{
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int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
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int s = (((lane & 1) != 0) ? DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT
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: DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
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uint8 l = dp->linkStatus[i - DP_LANE0_1_STATUS];
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return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
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}
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static uint8
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dp_get_adjust_request_pre_emphasis(dp_info* dp, int lane)
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{
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int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
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int s = (((lane & 1) != 0) ? DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT
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: DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
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uint8 l = dp->linkStatus[i - DP_LANE0_1_STATUS];
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return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
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}
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#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
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#define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5
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static void
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dp_get_adjust_train(dp_info* dp)
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{
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TRACE("%s\n", __func__);
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const char* voltageNames[] = {
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"0.4V", "0.6V", "0.8V", "1.2V"
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};
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const char* preEmphasisNames[] = {
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"0dB", "3.5dB", "6dB", "9.5dB"
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};
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uint8 voltage = 0;
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uint8 preEmphasis = 0;
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int lane;
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for (lane = 0; lane < dp->laneCount; lane++) {
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uint8 laneVoltage = dp_get_adjust_request_voltage(dp, lane);
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uint8 lanePreEmphasis = dp_get_adjust_request_pre_emphasis(dp, lane);
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TRACE("%s: Requested %s at %s for lane %d\n", __func__,
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preEmphasisNames[lanePreEmphasis >> DP_TRAIN_PRE_EMPHASIS_SHIFT],
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voltageNames[laneVoltage >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
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lane);
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if (laneVoltage > voltage)
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voltage = laneVoltage;
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if (lanePreEmphasis > preEmphasis)
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preEmphasis = lanePreEmphasis;
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}
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if (voltage >= DP_VOLTAGE_MAX)
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voltage |= DP_TRAIN_MAX_SWING_REACHED;
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if (preEmphasis >= DP_PRE_EMPHASIS_MAX)
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preEmphasis |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
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for (lane = 0; lane < 4; lane++)
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dp->trainingSet[lane] = voltage | preEmphasis;
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}
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static void
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dp_set_tp(dp_info* dp, int trainingPattern)
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{
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TRACE("%s\n", __func__);
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radeon_shared_info &info = *gInfo->shared_info;
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int rawTrainingPattern = 0;
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/* set training pattern on the source */
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if (info.dceMajor >= 4 || !dp->trainingUseEncoder) {
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switch (trainingPattern) {
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case DP_TRAINING_PATTERN_1:
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rawTrainingPattern = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
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break;
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case DP_TRAINING_PATTERN_2:
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rawTrainingPattern = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
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break;
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case DP_TRAINING_PATTERN_3:
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rawTrainingPattern = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
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break;
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}
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// TODO: PixelClock 0 ok?
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encoder_dig_setup(dp->connectorIndex, 0, rawTrainingPattern);
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} else {
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ERROR("%s: TODO: dp_encoder_service\n", __func__);
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return;
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#if 0
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switch (trainingPattern) {
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case DP_TRAINING_PATTERN_1:
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rawTrainingPattern = 0;
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break;
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case DP_TRAINING_PATTERN_2:
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rawTrainingPattern = 1;
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break;
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}
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radeon_dp_encoder_service(dp_info->rdev,
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ATOM_DP_ACTION_TRAINING_PATTERN_SEL, dp_info->dp_clock,
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dp_info->enc_id, rawTrainingPattern);
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#endif
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}
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// Enable training pattern on the sink
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dpcd_reg_write(dp->auxPin, DP_TRAINING_PATTERN_SET, trainingPattern);
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}
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status_t
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dp_link_train_cr(dp_info* dp)
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{
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TRACE("%s\n", __func__);
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// Display Port Clock Recovery Training
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bool clockRecovery = false;
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uint8 voltage = 0xff;
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int lane;
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dp_set_tp(dp, DP_TRAINING_PATTERN_1);
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memset(dp->trainingSet, 0, 4);
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dp_update_vs_emph(dp);
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while (1) {
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if (dp->trainingReadInterval == 0)
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snooze(100);
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else
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snooze(1000 * 4 * dp->trainingReadInterval);
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if (!dp_get_link_status(dp))
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break;
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if (dp_clock_recovery_ok(dp)) {
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clockRecovery = true;
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break;
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}
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for (lane = 0; lane < dp->laneCount; lane++) {
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if ((dp->trainingSet[lane] & DP_TRAIN_MAX_SWING_REACHED) == 0)
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break;
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}
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if (lane == dp->laneCount) {
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ERROR("%s: clock recovery reached max voltage\n", __func__);
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break;
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}
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if ((dp->trainingSet[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
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dp->trainingAttempts++;
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if (dp->trainingAttempts >= 5) {
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ERROR("%s: clock recovery tried 5 times\n", __func__);
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break;
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}
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} else
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dp->trainingAttempts = 0;
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voltage = dp->trainingSet[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
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// Compute new trainingSet as requested by sink
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dp_get_adjust_train(dp);
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dp_update_vs_emph(dp);
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}
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if (!clockRecovery) {
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ERROR("%s: clock recovery failed\n", __func__);
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return B_ERROR;
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}
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TRACE("%s: clock recovery at voltage %d pre-emphasis %d\n",
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__func__, dp->trainingSet[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
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(dp->trainingSet[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
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>> DP_TRAIN_PRE_EMPHASIS_SHIFT);
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return B_OK;
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}
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status_t
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dp_link_train(uint8 crtcID, display_mode* mode)
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{
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TRACE("%s\n", __func__);
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uint32 connectorIndex = gDisplay[crtcID]->connectorIndex;
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if (gDPInfo[connectorIndex]->valid != true) {
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ERROR("%s: started on non-DisplayPort connector #%" B_PRIu32 "\n",
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dp_info* dp = gDPInfo[connectorIndex];
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if (dp->valid != true) {
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ERROR("%s: started on invalid DisplayPort connector #%" B_PRIu32 "\n",
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__func__, connectorIndex);
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return B_ERROR;
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}
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@ -436,13 +679,13 @@ dp_link_train(uint8 crtcID, display_mode* mode)
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uint8 tableMajor;
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uint8 tableMinor;
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bool dpUseEncoder = true;
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dp->trainingUseEncoder = true;
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if (atom_parse_cmd_header(gAtomContext, index, &tableMajor, &tableMinor)
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== B_OK) {
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if (tableMinor > 1) {
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// The AtomBIOS DPEncoderService greater then 1.1 can't program the
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// training pattern properly.
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dpUseEncoder = false;
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dp->trainingUseEncoder = false;
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}
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}
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@ -461,22 +704,24 @@ dp_link_train(uint8 crtcID, display_mode* mode)
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else
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dpEncoderID |= ATOM_DP_CONFIG_LINK_A;
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//uint8 dpReadInterval = dpcd_reg_read(hwPin, DP_TRAINING_AUX_RD_INTERVAL);
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dp->trainingReadInterval
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= dpcd_reg_read(hwPin, DP_TRAINING_AUX_RD_INTERVAL);
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uint8 sandbox = dpcd_reg_read(hwPin, DP_MAX_LANE_COUNT);
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radeon_shared_info &info = *gInfo->shared_info;
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bool dpTPS3Supported = false;
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if (info.dceMajor >= 5 && (sandbox & DP_TPS3_SUPPORTED) != 0)
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dpTPS3Supported = true;
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//bool dpTPS3Supported = false;
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//if (info.dceMajor >= 5 && (sandbox & DP_TPS3_SUPPORTED) != 0)
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// dpTPS3Supported = true;
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// DisplayPort training initialization
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// *** DisplayPort link training initialization
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// Power up the DP sink
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if (gDPInfo[connectorIndex]->config[0] >= 0x11)
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if (dp->config[0] >= 0x11)
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dpcd_reg_write(hwPin, DP_SET_POWER, DP_SET_POWER_D0);
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// Possibly enable downspread on the sink
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if ((gDPInfo[connectorIndex]->config[3] & 0x1) != 0)
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if ((dp->config[3] & 0x1) != 0)
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dpcd_reg_write(hwPin, DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
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else
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dpcd_reg_write(hwPin, DP_DOWNSPREAD_CTRL, 0);
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@ -484,16 +729,16 @@ dp_link_train(uint8 crtcID, display_mode* mode)
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encoder_dig_setup(connectorIndex, mode->timing.pixel_clock,
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ATOM_ENCODER_CMD_SETUP_PANEL_MODE);
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if (gDPInfo[connectorIndex]->config[0] >= 0x11)
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if (dp->config[0] >= 0x11)
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sandbox |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
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dpcd_reg_write(hwPin, DP_LANE_COUNT_SET, sandbox);
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// Set the link rate on the DP sink
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sandbox = dp_get_link_clock_encode(gDPInfo[connectorIndex]->clock);
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sandbox = dp_get_link_clock_encode(dp->clock);
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dpcd_reg_write(hwPin, DP_LINK_BW_SET, sandbox);
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// Start link training on source
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if (info.dceMajor >= 4 || !dpUseEncoder) {
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if (info.dceMajor >= 4 || !dp->trainingUseEncoder) {
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encoder_dig_setup(connectorIndex, mode->timing.pixel_clock,
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ATOM_ENCODER_CMD_DP_LINK_TRAINING_START);
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} else {
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@ -501,21 +746,23 @@ dp_link_train(uint8 crtcID, display_mode* mode)
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__func__);
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}
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/* disable the training pattern on the sink */
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// Disable the training pattern on the sink
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dpcd_reg_write(hwPin, DP_TRAINING_PATTERN_SET,
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DP_TRAINING_PATTERN_DISABLE);
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// TODO: dp_link_train_cr
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dp_link_train_cr(dp);
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// TODO: dp_link_train_ce
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// *** DisplayPort link training finish
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snooze(400);
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/* disable the training pattern on the sink */
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// Disable the training pattern on the sink
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dpcd_reg_write(hwPin, DP_TRAINING_PATTERN_SET,
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DP_TRAINING_PATTERN_DISABLE);
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/* disable the training pattern on the source */
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if (info.dceMajor >= 4 || !dpUseEncoder) {
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// Disable the training pattern on the source
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if (info.dceMajor >= 4 || !dp->trainingUseEncoder) {
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encoder_dig_setup(connectorIndex, mode->timing.pixel_clock,
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ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE);
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} else {
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@ -13,6 +13,7 @@
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#include <stdint.h>
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#include <SupportDefs.h>
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#include "accelerant.h"
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#include "displayport_reg.h"
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@ -32,6 +33,7 @@ uint32 dp_get_link_clock_decode(uint32 dpLinkClock);
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void dp_setup_connectors();
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status_t dp_link_train(uint8 crtcID, display_mode* mode);
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status_t dp_link_train_cr(dp_info* dp);
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#endif /* RADEON_HD_DISPLAYPORT_H */
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@ -1069,8 +1069,12 @@ transmitter_dig_setup(uint32 connectorIndex, uint32 pixelClock,
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index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
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break;
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default:
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ERROR("%s: called on non-dig encoder!\n", __func__);
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return B_ERROR;
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// Multiple encoders can be wired to a single connector
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// An example is UNIPHY -> DP -> TRAVIS -> LVDS
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ERROR("%s: BUG: guessing UNIPHY as this isn't a dig encoder!\n",
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__func__);
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index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
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break;
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}
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if (index < 0) {
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