Add complete set of DRM DisplayPort defines into radeon_hd
* I'd rather this be common code, but I don't have access to the DisplayPort specifications. If I added it as common code I would want to be 100% it was complete and variables were named properly. * For now putting in radeon_hd private headers
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Alexander von Gluck IV
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cda904359e
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249495e284
160
headers/private/graphics/radeon_hd/displayport_reg.h
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160
headers/private/graphics/radeon_hd/displayport_reg.h
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/*
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* Copyright 2011, Haiku, Inc. All Rights Reserved.
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* Distributed under the terms of the MIT License.
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*
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* Authors:
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* Alexander von Gluck, kallisti5@unixzen.com
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*
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* DisplayPort DRM Specifications:
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* Copyright © 2008 Keith Packard
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*/
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#ifndef __DISPLAYPORT_REG_H__
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#define __DISPLAYPORT_REG_H__
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/* TODO: get access to DisplayPort specifications and
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* place this into graphic private common code
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*/
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#define AUX_NATIVE_WRITE 0x8
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#define AUX_NATIVE_READ 0x9
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#define AUX_I2C_WRITE 0x0
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#define AUX_I2C_READ 0x1
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#define AUX_I2C_STATUS 0x2
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#define AUX_I2C_MOT 0x4
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#define AUX_NATIVE_REPLY_ACK (0x0 << 4)
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#define AUX_NATIVE_REPLY_NACK (0x1 << 4)
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#define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
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#define AUX_NATIVE_REPLY_MASK (0x3 << 4)
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#define AUX_I2C_REPLY_ACK (0x0 << 6)
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#define AUX_I2C_REPLY_NACK (0x1 << 6)
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#define AUX_I2C_REPLY_DEFER (0x2 << 6)
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#define AUX_I2C_REPLY_MASK (0x3 << 6)
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// ** AUX channel addresses
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// * DisplayPort Configuration data
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#define DP_DPCD_REV 0x000
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#define DP_MAX_LINK_RATE 0x001
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#define DP_MAX_LANE_COUNT 0x002
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#define DP_MAX_LANE_COUNT_MASK 0x1f
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#define DP_TPS3_SUPPORTED (1 << 6)
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#define DP_ENHANCED_FRAME_CAP (1 << 7)
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#define DP_MAX_DOWNSPREAD 0x003
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#define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
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#define DP_NORP 0x004
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// Down stream DisplayPort status
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#define DP_DOWNSTREAMPORT_PRESENT 0x005
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# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
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# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
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// Down stream port types:
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// 00 = DisplayPort
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// 01 = Analog
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// 10 = TMDS or HDMI
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// 11 = Other
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#define DP_FORMAT_CONVERSION (1 << 3)
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#define DP_MAIN_LINK_CHANNEL_CODING 0x006
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#define DP_TRAINING_AUX_RD_INTERVAL 0x00e
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// DisplayPort link configuration
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#define DP_LINK_BW_SET 0x100
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#define DP_LINK_BW_1_62 0x06
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#define DP_LINK_BW_2_7 0x0a
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#define DP_LINK_BW_5_4 0x14
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#define DP_LANE_COUNT_SET 0x101
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#define DP_LANE_COUNT_MASK 0x0f
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#define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
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// DisplayPort training patern (used for link training)
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#define DP_TRAINING_PATTERN_SET 0x102
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#define DP_TRAINING_PATTERN_DISABLE 0
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#define DP_TRAINING_PATTERN_1 1
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#define DP_TRAINING_PATTERN_2 2
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#define DP_TRAINING_PATTERN_3 3
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#define DP_TRAINING_PATTERN_MASK 0x3
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#define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
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#define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
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#define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
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#define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
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#define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
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#define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
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#define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
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#define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
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#define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
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#define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
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#define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
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#define DP_TRAINING_LANE0_SET 0x103
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#define DP_TRAINING_LANE1_SET 0x104
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#define DP_TRAINING_LANE2_SET 0x105
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#define DP_TRAINING_LANE3_SET 0x106
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#define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
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#define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
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#define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
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#define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0)
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#define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0)
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#define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0)
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#define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0)
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#define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
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#define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3)
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#define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3)
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#define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3)
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#define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3)
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#define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
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#define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
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#define DP_DOWNSPREAD_CTRL 0x107
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#define DP_SPREAD_AMP_0_5 (1 << 4)
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#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
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#define DP_SET_ANSI_8B10B (1 << 0)
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#define DP_LANE0_1_STATUS 0x202
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#define DP_LANE2_3_STATUS 0x203
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#define DP_LANE_CR_DONE (1 << 0)
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#define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
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#define DP_LANE_SYMBOL_LOCKED (1 << 2)
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#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE \
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| DP_LANE_CHANNEL_EQ_DONE \
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| DP_LANE_SYMBOL_LOCKED)
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#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
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#define DP_INTERLANE_ALIGN_DONE (1 << 0)
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#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
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#define DP_LINK_STATUS_UPDATED (1 << 7)
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#define DP_SINK_STATUS 0x205
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#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
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#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
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#define DP_ADJUST_REQUEST_LANE0_1 0x206
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#define DP_ADJUST_REQUEST_LANE2_3 0x207
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#define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
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#define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
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#define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
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#define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
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#define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
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#define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
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#define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
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#define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
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#define DP_SET_POWER 0x600
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#define DP_SET_POWER_D0 0x1
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#endif /*__DISPLAYPORT_REG_H__*/
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@ -13,6 +13,7 @@
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#include "accelerant.h"
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#include "accelerant_protos.h"
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#include "displayport_reg.h"
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#undef TRACE
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@ -13,26 +13,6 @@
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#include <SupportDefs.h>
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// From the VESA DisplayPort spec
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// TODO: may want to move these into common code
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#define AUX_NATIVE_WRITE 0x8
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#define AUX_NATIVE_READ 0x9
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#define AUX_I2C_WRITE 0x0
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#define AUX_I2C_READ 0x1
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#define AUX_I2C_STATUS 0x2
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#define AUX_I2C_MOT 0x4
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#define AUX_NATIVE_REPLY_ACK (0x0 << 4)
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#define AUX_NATIVE_REPLY_NACK (0x1 << 4)
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#define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
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#define AUX_NATIVE_REPLY_MASK (0x3 << 4)
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#define AUX_I2C_REPLY_ACK (0x0 << 6)
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#define AUX_I2C_REPLY_NACK (0x1 << 6)
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#define AUX_I2C_REPLY_DEFER (0x2 << 6)
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#define AUX_I2C_REPLY_MASK (0x3 << 6)
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int dp_aux_write(uint32 hwLine, uint16 address, uint8* send,
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uint8 sendBytes, uint8 delay);
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int dp_aux_read(uint32 hwLine, uint16 address, uint8* recv,
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