* Add resolution and depth variables to softc (for use in X driver, although
depth detection is currently problematic),
* Store more information about various chip revisions,
* Implement ioctls to help the X driver detect device presence and geometry.
* lpt device is defined in MI place (dev/ppbus/files.ppbus), dev/ic/lpt.c
is included there too; dev/ic/lpt.c is not included if ppbus is
configured or if there is alternative platform lpt (like for pc532)
* g/c MD lpt definitions and custom puc/upc attachments,
glue moved to conf/files and dev/pci/files.pci respectively; remove
device lpt definition from dev/isa/files.isa
* add ppbus parport attribute, atppc device attachments, adjust plip and lpt
glue
interrupts and timer calibration yet is also attached at mainbus).
Introduce the INDY_R4600_CACHE config option, which more accurately describes
the code enabled by this option.
This renders #ifdef IPxx completely obsolete, thus we theoretically can unify
the GENERIC files if a workable load address relocation scheme can be found.
mace devices to their own mace/ directory. Alter conf/files.sgimips to
reflect this change in a sane manner (i.e., pull in dev/files.dev and
mace/files.mace when appropriate).
At the same time, allow crime_intr_establish() to fall through to
mace_intr_establish(). mace devices now call cpu_intr_establish().
* move all device-specific bitbanging to the device drivers in question --
i.e., the ip32 init code doesn't access the CRIME registers directly but
instead trusts the CRIME driver to DTRT. machdep.c is cleaner thereby.
* introduce int.c, which handles the interrupt-controller goo formerly
in ip2x.c.
* unify the CPU interrupt handler, with CRIME, INT2, and the various timer
handlers hooked in via pointers in the platform struct.
* eliminate ip2x.c and ip32.c. After the interrupt handler cleanup, the
actual platform-dependent code was so minimal (rev identification, mask level
initialization) that it made sense to move it into machdep.c
* "#ifdef DEBUG printf("foo"); #endif" becomes aprint_debug.
Tested on my ip22 and ip32. Discussed with pooka@, rafal@.
The recommended workaround is a 5-10ms delay before and after accesses.
Therefore, move the affected bus_space_* operations from bus.h to bus.c
and special-case MACE accesses.
CRIME accesses are not affected, so introduce SGIMIPS_BUS_SPACE_CRIME and
use it as the CRIME tag.
My ip32 seems a little bit happier with this change, and my ip22 didn't
notice the change.
fit inside one memory chunk.
Leave 1 page before kernel untouched as that's where our initial kernel
stack before we switch to proc0 stack is (fixes boot problems on my Indy
with small kernels).
virtual memory reservation and a private pool of memory pages -- by a scheme
based on memory pools.
This allows better utilization of memory because buffers can now be allocated
with a granularity finer than the system's native page size (useful for
filesystems with e.g. 1k or 2k fragment sizes). It also avoids fragmentation
of virtual to physical memory mappings (due to the former fixed virtual
address reservation) resulting in better utilization of MMU resources on some
platforms. Finally, the scheme is more flexible by allowing run-time decisions
on the amount of memory to be used for buffers.
On the other hand, the effectiveness of the LRU queue for buffer recycling
may be somewhat reduced compared to the traditional method since, due to the
nature of the pool based memory allocation, the actual least recently used
buffer may release its memory to a pool different from the one needed by a
newly allocated buffer. However, this effect will kick in only if the
system is under memory pressure.
- hpc1_hdd_{ctl,bufptr} and hpc3_hdd_{ctl,bufptr} are
established in hpcreg.h. All references to these fields
are updated with the exception of if_sq: (haltwo,
hpcdma). This makes reading the code and spotting bugs
easier.
- hpcdma.c was applying EOCHAIN to the wrong descriptor
word for the hpc1 case.
- I added scsi_max_xfer to the abstraction layer, and it
allows some crusty #defines in wdsc.c to be removed.
hpc1 now doesn't waste descriptors as it once did.
- hpcreg.h was updated to reflect the lack of XMITDONE
bit in hpc1. HPC1_REV15 added for a test in hpc.c
- hpc.c now verifies HPC1 revisions (1.0 vs 1.5) and
prints the output a little prettier ;)
- power interrupts shouldn't establish on non-IP22
platforms.
divergence between HPC revision 1.5 and revision 3.
The wdsc driver has been updated to reflect this layer (and may now work on
IP20). The sq driver needs a bit more work before it can be committed.
routine, as IP20 does not possess an IOC. This will eventually be moved into
a dedicated IOC driver that attaches its peripherals as children, but the
changes involved are too intrusive right now.
zs_get_chan_addr() to reflect this.
XXX hardcoded addresses are quite distasteful. This should be passed in
through consinit() -- to avoid conflicts with Ilpo's soon-to-be-committed
framebuffer driver, I'll hold off until his code hits the tree.
* if loading from cdrom, assume we're performing an install and
fix up bootpath/kernel to load the proper install kernel.
* maximum filename length in volume header is eight characters.
Change boot.elf to ip2xboot, boot.ip32 to ip3xboot, and boot
to aoutboot (which matches kernel naming scheme as well).
(with several cosmetic changes by me) which fixes O2 (IP32) support.
Now my R5000 O2 works fine in multiuser with on-board AIC7880 SCSIs
and several PCI network cards (but only on serial console yet).
L2 cache on R5000/Rm5200 is still disabled for now, but it will be
fixed later, hopefully.
See recent discussion on port-sgimips for details.
which is automatically included during kernel config, and add comments
to individual machine-dependant majors.* files to assign new MI majors
in MI file.
Range 0-191 is reserved for machine-specific assignments, range
192+ are MI assignments.
Follows recent discussion on tech-kern@
be inserted into ktrace records. The general change has been to replace
"struct proc *" with "struct lwp *" in various function prototypes, pass
the lwp through and use l_proc to get the process pointer when needed.
Bump the kernel rev up to 1.6V
enabled on amd64). Add a dmat64 field to various PCI attach structures,
and pass it down where needed. Implement a simple new function called
pci_dma64_available(pa) to test if 64bit DMA addresses may be used.
This returns 1 iff _PCI_HAVE_DMA64 is defined in <machine/pci_machdep.h>,
and there is more than 4G of memory.
for a boot device type; this gets the boot.ip32 booting a kernel off disk.
While here remove some unrolled string compares in favor of strncmp() to
make code more readable.
of KSEG0/1 mappable PCI window (the MEG_ALIGN macro was aligning to *16* MB
instead of *1* MB due to an extra 0 in the round-to constant). Also, allow
the PCI code to fix up all functions of a multifunction device; both from
Chris Sekiya, with a bit of massaging by me.
store absolute year rather than an offset -- this means the clock is now
consitent across the ARCS PROM, IRIX and NetBSD.
XXX: This attachment is now a mismoner, since it's a Dallas Semi RTC, not
a Motorola RTC. Should be renamed.
a buffer long enouth, with the padding bytes initialised.
Also pad to ETHER_MIN_LEN - ETHER_CRC_LEN, not ETHER_MIN_LEN (padded frames
were 4 bytes too long).
external cache enable bit -- this allows software to enable or disable the
(external) L2 cache on the R5k and Rm527x and the (external) L3 cache on
the Rm7k. If the (external) cache is disabled, treat it as if there were
no cache for the purposes of the cache setup code.
Also, update sgimips code to use the new name.
cd ${KERNSRCDIR}/${KERNARCHDIR}/compile && ${PRINTOBJDIR}
This is far simpler than the previous system, and more robust with
objdirs built via BSDOBJDIR.
The previous method of finding KERNOBJDIR when using BSDOBJDIR by
referencing _SRC_TOP_OBJ_ from another directory was extremely
fragile due to the depth first tree walk by <bsd.subdir.mk>, and
the caching of _SRC_TOP_OBJ_ (with MAKEOVERRIDES) which would be
empty on the *first* pass to create fresh objdirs.
This change requires adding sys/arch/*/compile/Makefile to create
the objdir in that directory, and descending into arch/*/compile
from arch/*/Makefile. Remove the now-unnecessary .keep_me files
whilst here.
Per lengthy discussion with Andrew Brown.
pass in an interrupt handle (which is currently to the CRIME interrupt the
device is attached to) so the interrupt handlers know which device was the
one looking for attention.
While here, fix up PCI interrupt routing for both the on-board devices and
the PCI slots -- even though there is only one PCI slot in the chasis, the
hardware can accomodate up to three and provides an interrupt mapping for
all the PCI interrupt pins for both the internal SCSI & PCI slot and the
two "extra" slots.
This merge changes the device switch tables from static array to
dynamically generated by config(8).
- All device switches is defined as a constant structure in device drivers.
- The new grammer ``device-major'' is introduced to ``files''.
device-major <prefix> char <num> [block <num>] [<rules>]
- All device major numbers must be listed up in port dependent majors.<arch>
by using this grammer.
- Added the new naming convention.
The name of the device switch must be <prefix>_[bc]devsw for auto-generation
of device switch tables.
- The backward compatibility of loading block/character device
switch by LKM framework is broken. This is necessary to convert
from block/character device major to device name in runtime and vice versa.
- The restriction to assign device major by LKM is completely removed.
We don't need to reserve LKM entries for dynamic loading of device switch.
- In compile time, device major numbers list is packed into the kernel and
the LKM framework will refer it to assign device major number dynamically.
counters. These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.
pmc(9) is meant to be a general interface. Initially, the Intel XScale
counters are the only ones supported.
be properly used by any misc. cloning device. While here, correct
a comment to indicate that "open" is the only entry point and that
everything else is handled with fileops.
isn't perfect (the NetBSD device units must match ARCS device numbers), but
it's better than randomly matching one of the devices. Fixes PR 16584 from
Scott G. Taylor.
the ECOFF version of boot produced by `objcopy'. Using elf2ecoff make it
work, so use that instead. Also, don't bother stripping the bootblocks on
install (as that confuses strip, at least for the ECOFF one, and since the
build already strips them).
NULL for root PCI busses. For busses behind a bridge, it points to
a persistent copy of the bridge's pcitag_t. This can be very useful
for machine-dependent PCI bus enumeration code.
* Implement a machine-dependent pci_enumerate_bus() for sparc64 which
uses OFW device nodes to enumerate the bus. When a PCI bus that is
behind a bridge is attached, pci_attach_hook() allocates a new PCI
chipset tag for the new bus and sets it's "curnode" to the OFW node
of the bridge. This is used as a starting point when enumerating
that bus. Root busses get the OFW node of the host bridge (psycho).
* Garbage-collect "ofpci" and "ofppb" from the sparc64 port.
to schedule clock interrupts at a fixed interval, rather scheduling
the next one based on the time of the arrival/servicing of the previous
clock interrupt. Also, pick up a trick from the sbmips port to convert
a division in ip22_clkread to a multiplication, since those are much
cheaper -- the details of that are described in Simon's commit (see
Message-Id: <20020306073437.1D2A8B004@cvs.netbsd.org>). Thanks to
Jason Thorpe and Dominic Sweetman's "See MIPS Run" (where I found
mention of this very subject while looking for something totally un-
related! 8-) for the clue about the source of the timekeeping problems.
For the IP32, where we have no clock-calibration code yet, use the CPU
frequency provided by ARCS instead; it beats a hard-coded value!
As an added bonus, most of the CPU-clock related stuff is now collected
together in cpu_info_store, rather than as a collection of unorganized
global variables.
generally translates to "high interrupt load") -- the old code re-enabled
interrupts in the machine-specific hardware interrupt handler causing the
handler to be re-entered, possible multiple times. Could lead to kernel
stack overflows, and all sorts of mysterious crashes/hangs as a result.
While here, fix up the IP32 interrupt handler code to also not re-enable
interrupts.
Thanks for ideas/comments go to Chuq and Stephen Ma.
* Pull in dev/mii/files.mii from conf/files, rather than playing
the magic "files include order" dance in N machine-dependent
configuration definitions.
become ippp (ISDN ppp) and irip (ISDN raw IP). The character device now
are called: /dev/isdn (isdnd <-> kernel communication), /dev/isdnctl (dialing
and other control), /dev/isdntrc* (tracing), /dev/isdnbchan* (raw B channel
access, i.e. for user land PPP) and /dev/isdntel* (telephone devices, i.e.
for answering machines).
deal with shortages of the VM maps where the backing pages are mapped
(usually kmem_map). Try to deal with this:
* Group all information about the backend allocator for a pool in a
separate structure. The pool references this structure, rather than
the individual fields.
* Change the pool_init() API accordingly, and adjust all callers.
* Link all pools using the same backend allocator on a list.
* The backend allocator is responsible for waiting for physical memory
to become available, but will still fail if it cannot callocate KVA
space for the pages. If this happens, carefully drain all pools using
the same backend allocator, so that some KVA space can be freed.
* Change pool_reclaim() to indicate if it actually succeeded in freeing
some pages, and use that information to make draining easier and more
efficient.
* Get rid of PR_URGENT. There was only one use of it, and it could be
dealt with by the caller.
From art@openbsd.org.
Be consistant in the way that MSIZE, MCLSHIFT, MCLBYTES and NMBCLUSTERS
are defined.
Remove old VM constants from cesfic port.
Bump MSIZE to 256 on mipsco (the only one that wasn't already 256).
