Add dedicated IOC (I/O Controller) driver. pckbc, zstty, and lpt will each
receive *_ioc.c attachments; machines without IOC (i.e., IP20) will use *_hpc.c stubs.
This commit is contained in:
sekiya
parent
7eec24689d
commit
aa10d0203e
6
sys/arch/sgimips/ioc/files.ioc
Normal file
6
sys/arch/sgimips/ioc/files.ioc
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@ -0,0 +1,6 @@
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# $NetBSD: files.ioc,v 1.1 2003/12/15 10:23:52 sekiya Exp $
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device ioc {[offset = -1], [intr = -1] }
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attach ioc at mainbus
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file arch/sgimips/ioc/ioc.c ioc
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227
sys/arch/sgimips/ioc/ioc.c
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227
sys/arch/sgimips/ioc/ioc.c
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@ -0,0 +1,227 @@
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/* $NetBSD: ioc.c,v 1.1 2003/12/15 10:23:52 sekiya Exp $ */
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/*
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* Copyright (c) 2003 Christopher Sekiya
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the
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* NetBSD Project. See http://www.NetBSD.org/ for
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* information about NetBSD.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* ip20/22/24 I/O Controller (IOC)
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ioc.c,v 1.1 2003/12/15 10:23:52 sekiya Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/callout.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <sys/ioctl.h>
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#include <sys/errno.h>
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#include <sys/syslog.h>
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#include <uvm/uvm_extern.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/locore.h>
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#include <machine/autoconf.h>
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#include <machine/machtype.h>
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#include <sgimips/ioc/iocreg.h>
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#include <sgimips/ioc/iocvar.h>
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#include "locators.h"
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struct ioc_softc {
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struct device sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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};
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static int ioc_match(struct device *, struct cfdata *, void *);
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static void ioc_attach(struct device *, struct device *, void *);
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#if defined(notyet)
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static int ioc_print(void *, const char *);
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static int ioc_search(struct device *, struct cfdata *, void *);
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#endif
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CFATTACH_DECL(ioc, sizeof(struct ioc_softc),
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ioc_match, ioc_attach, NULL, NULL);
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#if defined(BLINK)
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static struct callout ioc_blink_ch = CALLOUT_INITIALIZER;
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static void ioc_blink(void *);
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#endif
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static int
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ioc_match(struct device * parent, struct cfdata * match, void *aux)
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{
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if (mach_type == MACH_SGI_IP22)
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return 1;
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return 0;
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}
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static void
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ioc_attach(struct device * parent, struct device * self, void *aux)
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{
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struct ioc_softc *sc = (struct ioc_softc *) self;
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struct mainbus_attach_args *maa = aux;
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u_int32_t sysid;
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sc->sc_iot = SGIMIPS_BUS_SPACE_HPC;
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if (bus_space_map(sc->sc_iot, maa->ma_addr, 0,
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BUS_SPACE_MAP_LINEAR, &sc->sc_ioh))
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panic("ioc_attach: could not allocate memory\n");
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sysid = bus_space_read_4(sc->sc_iot, sc->sc_ioh, IOC_SYSID) & 0x01;
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if (sysid)
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mach_subtype = MACH_SGI_IP22_FULLHOUSE;
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else
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mach_subtype = MACH_SGI_IP22_GUINESS;
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aprint_normal(": rev %d, machine %s, board rev %d\n",
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((sysid & IOC_SYSID_CHIPREV) >> IOC_SYSID_CHIPREV_SHIFT),
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(sysid & IOC_SYSID_SYSTYPE) ? "Indigo2 (Fullhouse)" : "Indy (Guiness)",
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((sysid & IOC_SYSID_BOARDREV) >> IOC_SYSID_BOARDREV_SHIFT));
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/* Reset IOC */
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, IOC_RESET,
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IOC_RESET_PARALLEL | IOC_RESET_PCKBC |
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IOC_RESET_EISA | IOC_RESET_ISDN |
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IOC_RESET_LED_GREEN );
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/*
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* Set the 10BaseT port to use UTP cable, set autoselect mode for
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* the ethernet interface (AUI vs. TP), set the two serial ports
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* to PC mode.
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*/
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, IOC_WRITE,
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IOC_WRITE_ENET_AUTO | IOC_WRITE_ENET_UTP |
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IOC_WRITE_PC_UART2 | IOC_WRITE_PC_UART1);
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if (mach_subtype == MACH_SGI_IP22_GUINESS) {
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, IOC_GCSEL, 0xff);
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, IOC_GCREG, 0xff);
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}
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#if defined(BLINK)
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ioc_blink(sc);
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#endif
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#if defined(notyet)
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/*
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* pckbc, zstty, and lpt should attach under the IOC. This begs the
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* question of how we sort things out with ip20, which has no IOC.
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* For now, we pretend that everything attaches at HPC and ignore
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* the IOC.
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*/
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config_search(ioc_search, self, NULL);
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#endif
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}
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#if defined(notyet)
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static int
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ioc_print(void *aux, const char *pnp)
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{
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struct ioc_attach_args *iaa = aux;
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if (pnp != 0)
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return QUIET;
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if (iaa->iaa_offset != IOCCF_OFFSET_DEFAULT)
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aprint_normal(" offset 0x%lx", iaa->iaa_offset);
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if (iaa->iaa_intr != IOCCF_INTR_DEFAULT)
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aprint_normal(" intr %d", iaa->iaa_intr);
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return UNCONF;
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}
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static int
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ioc_search(struct device * parent, struct cfdata * cf, void *aux)
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{
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struct ioc_softc *sc = (struct ioc_softc *) parent;
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struct ioc_attach_args iaa;
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int tryagain;
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do {
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iaa.iaa_offset = cf->cf_loc[IOCCF_OFFSET];
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iaa.iaa_intr = cf->cf_loc[IOCCF_INTR];
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iaa.iaa_st = SGIMIPS_BUS_SPACE_HPC;
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iaa.iaa_sh = sc->sc_ioh; /* XXX */
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tryagain = 0;
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if (config_match(parent, cf, &iaa) > 0) {
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config_attach(parent, cf, &iaa, ioc_print);
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tryagain = (cf->cf_fstate == FSTATE_STAR);
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}
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} while (tryagain);
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return 0;
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}
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#endif
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#if defined(BLINK)
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static void
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ioc_blink(void *self)
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{
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struct ioc_softc *sc = (struct ioc_softc *) self;
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register int s;
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int value;
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s = splhigh();
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/* This is a bit odd. To strobe the green LED, we have to toggle the
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red control bit. */
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value = bus_space_read_4(sc->sc_iot, sc->sc_ioh, IOC_RESET) & 0xff;
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value ^= IOC_RESET_LED_RED;
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, IOC_RESET, value);
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splx(s);
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/*
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* Blink rate is:
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* full cycle every second if completely idle (loadav = 0)
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* full cycle every 2 seconds if loadav = 1
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* full cycle every 3 seconds if loadav = 2
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* etc.
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*/
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s = (((averunnable.ldavg[0] + FSCALE) * hz) >> (FSHIFT + 1));
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callout_reset(&ioc_blink_ch, s, ioc_blink, sc);
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}
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#endif
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124
sys/arch/sgimips/ioc/iocreg.h
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124
sys/arch/sgimips/ioc/iocreg.h
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@ -0,0 +1,124 @@
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/* $NetBSD: iocreg.h,v 1.1 2003/12/15 10:23:52 sekiya Exp $ */
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/*
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* Copyright (c) 2003 Christopher Sekiya
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* Copyright (c) 2001 Rafal K. Boni
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARCH_SGIMIPS_IOC_IOCREG_H_
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#define _ARCH_SGIMIPS_IOC_IOCREG_H_
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/*
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* IOC1/2 memory map.
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*
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* The IOC1/2 is connected to the HPC#0, PBus channel 6, so these registers
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* are based from the external register window for PBus channel 6 on HPC#0.
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*
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*/
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#define IOC_PLP_REGS 0x00 /* Parallel port registers */
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#define IOC_PLP_REGS_SIZE 0x2c
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#define IOC_PLP_DATA 0x00 /* Data register */
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#define IOC_PLP_CTL 0x04 /* Control register */
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#define IOC_PLP_STAT 0x08 /* Status register */
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#define IOC_PLP_DMACTL 0x0c /* DMA control register */
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#define IOC_PLP_INTSTAT 0x10 /* Interrupt status register */
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#define IOC_PLP_INTMASK 0x14 /* Interrupt mask register */
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#define IOC_PLP_TIMER1 0x18 /* Timer 1 register */
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#define IOC_PLP_TIMER2 0x1c /* Timer 2 register */
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#define IOC_PLP_TIMER3 0x20 /* Timer 3 register */
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#define IOC_PLP_TIMER4 0x24 /* Timer 4 register */
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#define IOC_SERIAL_REGS 0x30 /* Serial port registers */
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#define IOC_SERIAL_REGS_SIZE 0x0c
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#define IOC_SERIAL_PORT1_CMD 0x00 /* Port 1 command transfer */
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#define IOC_SERIAL_PORT1_DATA 0x04 /* Port 1 data transfer */
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#define IOC_SERIAL_PORT2_CMD 0x08 /* Port 2 command transfer */
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#define IOC_SERIAL_PORT2_DATA 0x0c /* Port 2 data transfer */
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#define IOC_KB_REGS 0x40 /* Keyboard/mouse registers */
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#define IOC_KB_REGS_SIZE 0x08
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/* Miscellaneous registers */
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#define IOC_MISC_REGS 0x48 /* Misc. IOC regs */
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#define IOC_MISC_REGS_SIZE 0x34
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#define IOC_GCSEL 0x48 /* General select register */
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#define IOC_GCREG 0x4c /* General control register */
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#define IOC_PANEL 0x50 /* Front Panel register */
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#define IOC_PANEL_POWER_STATE 0x01
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#define IOC_PANEL_POWER_IRQ 0x02
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#define IOC_PANEL_VDOWN_IRQ 0x10
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#define IOC_PANEL_VDOWN_HOLD 0x20
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#define IOC_PANEL_VUP_IRQ 0x40
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#define IOC_PANEL_VUP_HOLD 0x80
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#define IOC_SYSID 0x58 /* System ID register */
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#define IOC_SYSID_SYSTYPE 0x01 /* 0: Sapphire, 1: Full House */
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#define IOC_SYSID_BOARDREV 0x1e
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#define IOC_SYSID_BOARDREV_SHIFT 1
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#define IOC_SYSID_CHIPREV 0xe0
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#define IOC_SYSID_CHIPREV_SHIFT 5
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#define IOC_READ 0x60 /* Read register */
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#define IOC_READ_SCSI0_POWER 0x10
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#define IOC_READ_SCSI1_POWER 0x20
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#define IOC_READ_ENET_POWER 0x40
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#define IOC_READ_ENET_LINK 0x80
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#define IOC_DMASEL 0x68 /* DMA select register */
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#define IOC_DMASEL_ISDN_B 0x01
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#define IOC_DMASEL_ISDN_A 0x02
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#define IOC_DMASEL_PARALLEL 0x04
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#define IOC_DMASEL_SERIAL_10MHZ 0x00
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#define IOC_DMASEL_SERIAL_6MHZ 0x10
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#define IOC_DMASEL_SERIAL_EXTERNAL 0x20
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#define IOC_RESET 0x70 /* Reset register */
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#define IOC_RESET_PARALLEL 0x01
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#define IOC_RESET_PCKBC 0x02
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#define IOC_RESET_EISA 0x04
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#define IOC_RESET_ISDN 0x08
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#define IOC_RESET_LED_GREEN 0x10
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#define IOC_RESET_LED_RED 0x20
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#define IOC_RESET_LED_ORANGE 0x40
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#define IOC_WRITE 0x78 /* Write register */
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#define IOC_WRITE_ENET_NTH 0x01
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#define IOC_WRITE_ENET_UTP 0x02
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#define IOC_WRITE_ENET_AUI 0x04
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#define IOC_WRITE_ENET_AUTO 0x08
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#define IOC_WRITE_PC_UART2 0x10
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#define IOC_WRITE_PC_UART1 0x20
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#define IOC_WRITE_MARGIN_LOW 0x40
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#define IOC_WRITE_MARGIN_HIGH 0x80
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#endif /* _ARCH_SGIMIPS_IOC_IOCREG_H_ */
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42
sys/arch/sgimips/ioc/iocvar.h
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42
sys/arch/sgimips/ioc/iocvar.h
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@ -0,0 +1,42 @@
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/* $NetBSD: iocvar.h,v 1.1 2003/12/15 10:23:52 sekiya Exp $ */
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/*
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* Copyright (c) 2003 Christopher Sekiya
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* All rights reserved.
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*
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||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed for the
|
||||
* NetBSD Project. See http://www.NetBSD.org/ for
|
||||
* information about NetBSD.
|
||||
* 4. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
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struct ioc_attach_args {
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bus_space_tag_t iaa_st;
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bus_space_handle_t iaa_sh;
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bus_dma_tag_t iaa_dmat;
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long iaa_offset;
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int iaa_intr;
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};
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