diff --git a/sys/arch/sgimips/ioc/files.ioc b/sys/arch/sgimips/ioc/files.ioc new file mode 100644 index 000000000000..8fc98860955a --- /dev/null +++ b/sys/arch/sgimips/ioc/files.ioc @@ -0,0 +1,6 @@ +# $NetBSD: files.ioc,v 1.1 2003/12/15 10:23:52 sekiya Exp $ + +device ioc {[offset = -1], [intr = -1] } +attach ioc at mainbus +file arch/sgimips/ioc/ioc.c ioc + diff --git a/sys/arch/sgimips/ioc/ioc.c b/sys/arch/sgimips/ioc/ioc.c new file mode 100644 index 000000000000..1c6a2651ca9d --- /dev/null +++ b/sys/arch/sgimips/ioc/ioc.c @@ -0,0 +1,227 @@ +/* $NetBSD: ioc.c,v 1.1 2003/12/15 10:23:52 sekiya Exp $ */ + +/* + * Copyright (c) 2003 Christopher Sekiya + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the + * NetBSD Project. See http://www.NetBSD.org/ for + * information about NetBSD. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ip20/22/24 I/O Controller (IOC) + */ + +#include +__KERNEL_RCSID(0, "$NetBSD: ioc.c,v 1.1 2003/12/15 10:23:52 sekiya Exp $"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "locators.h" + +struct ioc_softc { + struct device sc_dev; + + bus_space_tag_t sc_iot; + bus_space_handle_t sc_ioh; +}; + +static int ioc_match(struct device *, struct cfdata *, void *); +static void ioc_attach(struct device *, struct device *, void *); +#if defined(notyet) +static int ioc_print(void *, const char *); +static int ioc_search(struct device *, struct cfdata *, void *); +#endif + +CFATTACH_DECL(ioc, sizeof(struct ioc_softc), + ioc_match, ioc_attach, NULL, NULL); + +#if defined(BLINK) +static struct callout ioc_blink_ch = CALLOUT_INITIALIZER; +static void ioc_blink(void *); +#endif + +static int +ioc_match(struct device * parent, struct cfdata * match, void *aux) +{ + if (mach_type == MACH_SGI_IP22) + return 1; + + return 0; +} + +static void +ioc_attach(struct device * parent, struct device * self, void *aux) +{ + struct ioc_softc *sc = (struct ioc_softc *) self; + struct mainbus_attach_args *maa = aux; + u_int32_t sysid; + + sc->sc_iot = SGIMIPS_BUS_SPACE_HPC; + + if (bus_space_map(sc->sc_iot, maa->ma_addr, 0, + BUS_SPACE_MAP_LINEAR, &sc->sc_ioh)) + panic("ioc_attach: could not allocate memory\n"); + + sysid = bus_space_read_4(sc->sc_iot, sc->sc_ioh, IOC_SYSID) & 0x01; + + if (sysid) + mach_subtype = MACH_SGI_IP22_FULLHOUSE; + else + mach_subtype = MACH_SGI_IP22_GUINESS; + + aprint_normal(": rev %d, machine %s, board rev %d\n", + ((sysid & IOC_SYSID_CHIPREV) >> IOC_SYSID_CHIPREV_SHIFT), + (sysid & IOC_SYSID_SYSTYPE) ? "Indigo2 (Fullhouse)" : "Indy (Guiness)", + ((sysid & IOC_SYSID_BOARDREV) >> IOC_SYSID_BOARDREV_SHIFT)); + + /* Reset IOC */ + bus_space_write_4(sc->sc_iot, sc->sc_ioh, IOC_RESET, + IOC_RESET_PARALLEL | IOC_RESET_PCKBC | + IOC_RESET_EISA | IOC_RESET_ISDN | + IOC_RESET_LED_GREEN ); + + /* + * Set the 10BaseT port to use UTP cable, set autoselect mode for + * the ethernet interface (AUI vs. TP), set the two serial ports + * to PC mode. + */ + bus_space_write_4(sc->sc_iot, sc->sc_ioh, IOC_WRITE, + IOC_WRITE_ENET_AUTO | IOC_WRITE_ENET_UTP | + IOC_WRITE_PC_UART2 | IOC_WRITE_PC_UART1); + + if (mach_subtype == MACH_SGI_IP22_GUINESS) { + bus_space_write_4(sc->sc_iot, sc->sc_ioh, IOC_GCSEL, 0xff); + bus_space_write_4(sc->sc_iot, sc->sc_ioh, IOC_GCREG, 0xff); + } + +#if defined(BLINK) + ioc_blink(sc); +#endif + +#if defined(notyet) + /* + * pckbc, zstty, and lpt should attach under the IOC. This begs the + * question of how we sort things out with ip20, which has no IOC. + * For now, we pretend that everything attaches at HPC and ignore + * the IOC. + */ + + config_search(ioc_search, self, NULL); +#endif +} + +#if defined(notyet) +static int +ioc_print(void *aux, const char *pnp) +{ + struct ioc_attach_args *iaa = aux; + + if (pnp != 0) + return QUIET; + + if (iaa->iaa_offset != IOCCF_OFFSET_DEFAULT) + aprint_normal(" offset 0x%lx", iaa->iaa_offset); + if (iaa->iaa_intr != IOCCF_INTR_DEFAULT) + aprint_normal(" intr %d", iaa->iaa_intr); + + return UNCONF; +} + +static int +ioc_search(struct device * parent, struct cfdata * cf, void *aux) +{ + struct ioc_softc *sc = (struct ioc_softc *) parent; + struct ioc_attach_args iaa; + int tryagain; + + do { + iaa.iaa_offset = cf->cf_loc[IOCCF_OFFSET]; + iaa.iaa_intr = cf->cf_loc[IOCCF_INTR]; + iaa.iaa_st = SGIMIPS_BUS_SPACE_HPC; + iaa.iaa_sh = sc->sc_ioh; /* XXX */ + + tryagain = 0; + if (config_match(parent, cf, &iaa) > 0) { + config_attach(parent, cf, &iaa, ioc_print); + tryagain = (cf->cf_fstate == FSTATE_STAR); + } + } while (tryagain); + + return 0; +} +#endif + +#if defined(BLINK) +static void +ioc_blink(void *self) +{ + struct ioc_softc *sc = (struct ioc_softc *) self; + register int s; + int value; + + s = splhigh(); + + /* This is a bit odd. To strobe the green LED, we have to toggle the + red control bit. */ + + value = bus_space_read_4(sc->sc_iot, sc->sc_ioh, IOC_RESET) & 0xff; + value ^= IOC_RESET_LED_RED; + bus_space_write_4(sc->sc_iot, sc->sc_ioh, IOC_RESET, value); + splx(s); + /* + * Blink rate is: + * full cycle every second if completely idle (loadav = 0) + * full cycle every 2 seconds if loadav = 1 + * full cycle every 3 seconds if loadav = 2 + * etc. + */ + s = (((averunnable.ldavg[0] + FSCALE) * hz) >> (FSHIFT + 1)); + callout_reset(&ioc_blink_ch, s, ioc_blink, sc); + +} +#endif diff --git a/sys/arch/sgimips/ioc/iocreg.h b/sys/arch/sgimips/ioc/iocreg.h new file mode 100644 index 000000000000..fa4730d50f34 --- /dev/null +++ b/sys/arch/sgimips/ioc/iocreg.h @@ -0,0 +1,124 @@ +/* $NetBSD: iocreg.h,v 1.1 2003/12/15 10:23:52 sekiya Exp $ */ + +/* + * Copyright (c) 2003 Christopher Sekiya + * Copyright (c) 2001 Rafal K. Boni + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ARCH_SGIMIPS_IOC_IOCREG_H_ +#define _ARCH_SGIMIPS_IOC_IOCREG_H_ + +/* + * IOC1/2 memory map. + * + * The IOC1/2 is connected to the HPC#0, PBus channel 6, so these registers + * are based from the external register window for PBus channel 6 on HPC#0. + * + */ + +#define IOC_PLP_REGS 0x00 /* Parallel port registers */ +#define IOC_PLP_REGS_SIZE 0x2c + +#define IOC_PLP_DATA 0x00 /* Data register */ +#define IOC_PLP_CTL 0x04 /* Control register */ +#define IOC_PLP_STAT 0x08 /* Status register */ +#define IOC_PLP_DMACTL 0x0c /* DMA control register */ +#define IOC_PLP_INTSTAT 0x10 /* Interrupt status register */ +#define IOC_PLP_INTMASK 0x14 /* Interrupt mask register */ +#define IOC_PLP_TIMER1 0x18 /* Timer 1 register */ +#define IOC_PLP_TIMER2 0x1c /* Timer 2 register */ +#define IOC_PLP_TIMER3 0x20 /* Timer 3 register */ +#define IOC_PLP_TIMER4 0x24 /* Timer 4 register */ + +#define IOC_SERIAL_REGS 0x30 /* Serial port registers */ +#define IOC_SERIAL_REGS_SIZE 0x0c + +#define IOC_SERIAL_PORT1_CMD 0x00 /* Port 1 command transfer */ +#define IOC_SERIAL_PORT1_DATA 0x04 /* Port 1 data transfer */ +#define IOC_SERIAL_PORT2_CMD 0x08 /* Port 2 command transfer */ +#define IOC_SERIAL_PORT2_DATA 0x0c /* Port 2 data transfer */ + +#define IOC_KB_REGS 0x40 /* Keyboard/mouse registers */ +#define IOC_KB_REGS_SIZE 0x08 + +/* Miscellaneous registers */ + +#define IOC_MISC_REGS 0x48 /* Misc. IOC regs */ +#define IOC_MISC_REGS_SIZE 0x34 + +#define IOC_GCSEL 0x48 /* General select register */ + +#define IOC_GCREG 0x4c /* General control register */ + +#define IOC_PANEL 0x50 /* Front Panel register */ +#define IOC_PANEL_POWER_STATE 0x01 +#define IOC_PANEL_POWER_IRQ 0x02 +#define IOC_PANEL_VDOWN_IRQ 0x10 +#define IOC_PANEL_VDOWN_HOLD 0x20 +#define IOC_PANEL_VUP_IRQ 0x40 +#define IOC_PANEL_VUP_HOLD 0x80 + +#define IOC_SYSID 0x58 /* System ID register */ +#define IOC_SYSID_SYSTYPE 0x01 /* 0: Sapphire, 1: Full House */ +#define IOC_SYSID_BOARDREV 0x1e +#define IOC_SYSID_BOARDREV_SHIFT 1 +#define IOC_SYSID_CHIPREV 0xe0 +#define IOC_SYSID_CHIPREV_SHIFT 5 + +#define IOC_READ 0x60 /* Read register */ +#define IOC_READ_SCSI0_POWER 0x10 +#define IOC_READ_SCSI1_POWER 0x20 +#define IOC_READ_ENET_POWER 0x40 +#define IOC_READ_ENET_LINK 0x80 + +#define IOC_DMASEL 0x68 /* DMA select register */ +#define IOC_DMASEL_ISDN_B 0x01 +#define IOC_DMASEL_ISDN_A 0x02 +#define IOC_DMASEL_PARALLEL 0x04 +#define IOC_DMASEL_SERIAL_10MHZ 0x00 +#define IOC_DMASEL_SERIAL_6MHZ 0x10 +#define IOC_DMASEL_SERIAL_EXTERNAL 0x20 + +#define IOC_RESET 0x70 /* Reset register */ +#define IOC_RESET_PARALLEL 0x01 +#define IOC_RESET_PCKBC 0x02 +#define IOC_RESET_EISA 0x04 +#define IOC_RESET_ISDN 0x08 +#define IOC_RESET_LED_GREEN 0x10 +#define IOC_RESET_LED_RED 0x20 +#define IOC_RESET_LED_ORANGE 0x40 + +#define IOC_WRITE 0x78 /* Write register */ +#define IOC_WRITE_ENET_NTH 0x01 +#define IOC_WRITE_ENET_UTP 0x02 +#define IOC_WRITE_ENET_AUI 0x04 +#define IOC_WRITE_ENET_AUTO 0x08 +#define IOC_WRITE_PC_UART2 0x10 +#define IOC_WRITE_PC_UART1 0x20 +#define IOC_WRITE_MARGIN_LOW 0x40 +#define IOC_WRITE_MARGIN_HIGH 0x80 + +#endif /* _ARCH_SGIMIPS_IOC_IOCREG_H_ */ diff --git a/sys/arch/sgimips/ioc/iocvar.h b/sys/arch/sgimips/ioc/iocvar.h new file mode 100644 index 000000000000..4fda0cbedc2f --- /dev/null +++ b/sys/arch/sgimips/ioc/iocvar.h @@ -0,0 +1,42 @@ +/* $NetBSD: iocvar.h,v 1.1 2003/12/15 10:23:52 sekiya Exp $ */ + +/* + * Copyright (c) 2003 Christopher Sekiya + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the + * NetBSD Project. See http://www.NetBSD.org/ for + * information about NetBSD. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +struct ioc_attach_args { + bus_space_tag_t iaa_st; + bus_space_handle_t iaa_sh; + bus_dma_tag_t iaa_dmat; + + long iaa_offset; + int iaa_intr; +};