Adapt if_sq to HPC abstraction layer. It took both Steve Rumble and myself
to untangle the unhappiness that arises from the design differences between HPC1 and HPC3.
This commit is contained in:
sekiya
parent
52063657cc
commit
a072684caa
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@ -1,4 +1,4 @@
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/* $NetBSD: if_sq.c,v 1.19 2003/10/30 23:05:56 matt Exp $ */
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/* $NetBSD: if_sq.c,v 1.20 2003/12/30 23:48:07 sekiya Exp $ */
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/*
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* Copyright (c) 2001 Rafal K. Boni
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@ -33,7 +33,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_sq.c,v 1.19 2003/10/30 23:05:56 matt Exp $");
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__KERNEL_RCSID(0, "$NetBSD: if_sq.c,v 1.20 2003/12/30 23:48:07 sekiya Exp $");
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#include "bpfilter.h"
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@ -83,19 +83,24 @@ __KERNEL_RCSID(0, "$NetBSD: if_sq.c,v 1.19 2003/10/30 23:05:56 matt Exp $");
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* contiguous mbuf.
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* (3) Verify sq_stop() turns off enough stuff; I was still getting
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* seeq interrupts after sq_stop().
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* (4) Fix up printfs in driver (most should only fire ifdef SQ_DEBUG
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* or something similar.
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* (5) Implement EDLC modes: especially packet auto-pad and simplex
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* (4) Implement EDLC modes: especially packet auto-pad and simplex
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* mode.
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* (6) Should the driver filter out its own transmissions in non-EDLC
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* (5) Should the driver filter out its own transmissions in non-EDLC
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* mode?
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* (7) Multicast support -- multicast filter, address management, ...
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* (8) Deal with RB0 (recv buffer overflow) on reception. Will need
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* (6) Multicast support -- multicast filter, address management, ...
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* (7) Deal with RB0 (recv buffer overflow) on reception. Will need
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* to figure out if RB0 is read-only as stated in one spot in the
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* HPC spec or read-write (ie, is the 'write a one to clear it')
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* the correct thing?
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*/
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#if defined(SQ_DEBUG)
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int sq_debug = 0;
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#define SQ_DPRINTF(x) if (sq_debug) printf x
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#else
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#define SQ_DPRINTF(x)
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#endif
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static int sq_match(struct device *, struct cfdata *, void *);
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static void sq_attach(struct device *, struct device *, void *);
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static int sq_init(struct ifnet *);
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@ -174,9 +179,11 @@ sq_attach(struct device *parent, struct device *self, void *aux)
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struct ifnet *ifp = &sc->sc_ethercom.ec_if;
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sc->sc_hpct = haa->ha_st;
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sc->hpc_regs = haa->hpc_regs; /* HPC register definitions */
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if ((err = bus_space_subregion(haa->ha_st, haa->ha_sh,
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haa->ha_dmaoff,
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HPC_ENET_REGS_SIZE,
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sc->hpc_regs->enet_regs_size,
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&sc->sc_hpch)) != 0) {
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printf(": unable to map HPC DMA registers, error = %d\n", err);
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goto fail_0;
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@ -185,7 +192,7 @@ sq_attach(struct device *parent, struct device *self, void *aux)
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sc->sc_regt = haa->ha_st;
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if ((err = bus_space_subregion(haa->ha_st, haa->ha_sh,
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haa->ha_devoff,
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HPC_ENET_DEVREGS_SIZE,
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sc->hpc_regs->enet_devregs_size,
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&sc->sc_regh)) != 0) {
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printf(": unable to map Seeq registers, error = %d\n", err);
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goto fail_0;
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@ -237,7 +244,7 @@ sq_attach(struct device *parent, struct device *self, void *aux)
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}
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}
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/* Create transmit buffer DMA maps */
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/* Create receive buffer DMA maps */
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for (i = 0; i < SQ_NRXDESC; i++) {
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if ((err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES,
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0, BUS_DMA_NOWAIT,
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@ -396,19 +403,23 @@ sq_init(struct ifnet *ifp)
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bus_space_write_1(sc->sc_regt, sc->sc_regh, SEEQ_RXCMD, sc->sc_rxcmd);
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/* Set up HPC ethernet DMA config */
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reg = bus_space_read_4(sc->sc_hpct, sc->sc_hpch, HPC_ENETR_DMACFG);
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch, HPC_ENETR_DMACFG,
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if (sc->hpc_regs->revision == 3) {
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reg = bus_space_read_4(sc->sc_hpct, sc->sc_hpch,
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sc->hpc_regs->enetr_dmacfg);
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch,
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sc->hpc_regs->enetr_dmacfg,
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reg | ENETR_DMACFG_FIX_RXDC |
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ENETR_DMACFG_FIX_INTR |
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ENETR_DMACFG_FIX_EOP);
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}
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/* Pass the start of the receive ring to the HPC */
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch, HPC_ENETR_NDBP,
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch, sc->hpc_regs->enetr_ndbp,
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SQ_CDRXADDR(sc, 0));
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/* And turn on the HPC ethernet receive channel */
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch, HPC_ENETR_CTL,
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ENETR_CTL_ACTIVE);
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch, sc->hpc_regs->enetr_ctl,
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sc->hpc_regs->enetr_ctl_active);
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ifp->if_flags |= IFF_RUNNING;
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ifp->if_flags &= ~IFF_OACTIVE;
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@ -607,10 +618,17 @@ sq_start(struct ifnet *ifp)
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for (nexttx = sc->sc_nexttx, seg = 0, totlen = 0;
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seg < dmamap->dm_nsegs;
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seg++, nexttx = SQ_NEXTTX(nexttx)) {
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sc->sc_txdesc[nexttx].hdd_bufptr =
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if (sc->hpc_regs->revision == 3) {
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sc->sc_txdesc[nexttx].hpc3_hdd_bufptr =
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dmamap->dm_segs[seg].ds_addr;
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sc->sc_txdesc[nexttx].hdd_ctl =
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sc->sc_txdesc[nexttx].hpc3_hdd_ctl =
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dmamap->dm_segs[seg].ds_len;
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} else {
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sc->sc_txdesc[nexttx].hpc1_hdd_bufptr =
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dmamap->dm_segs[seg].ds_addr;
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sc->sc_txdesc[nexttx].hpc1_hdd_ctl =
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dmamap->dm_segs[seg].ds_len;
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}
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sc->sc_txdesc[nexttx].hdd_descptr=
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SQ_CDTXADDR(sc, SQ_NEXTTX(nexttx));
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lasttx = nexttx;
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/* Last descriptor gets end-of-packet */
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KASSERT(lasttx != -1);
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sc->sc_txdesc[lasttx].hdd_ctl |= HDD_CTL_EOPACKET;
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if (sc->hpc_regs->revision == 3)
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sc->sc_txdesc[lasttx].hpc3_hdd_ctl |= HDD_CTL_EOPACKET;
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else
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sc->sc_txdesc[lasttx].hpc1_hdd_ctl |=
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HPC1_HDD_CTL_EOPACKET;
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#if 0
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printf("%s: transmit %d-%d, len %d\n", sc->sc_dev.dv_xname,
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SQ_DPRINTF(("%s: transmit %d-%d, len %d\n", sc->sc_dev.dv_xname,
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sc->sc_nexttx, lasttx,
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totlen);
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#endif
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totlen));
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if (ifp->if_flags & IFF_DEBUG) {
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printf(" transmit chain:\n");
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for (seg = sc->sc_nexttx;; seg = SQ_NEXTTX(seg)) {
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printf(" descriptor %d:\n", seg);
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printf(" hdd_bufptr: 0x%08x\n",
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sc->sc_txdesc[seg].hdd_bufptr);
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(sc->hpc_regs->revision == 3) ?
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sc->sc_txdesc[seg].hpc3_hdd_bufptr :
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sc->sc_txdesc[seg].hpc1_hdd_bufptr);
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printf(" hdd_ctl: 0x%08x\n",
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sc->sc_txdesc[seg].hdd_ctl);
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(sc->hpc_regs->revision == 3) ?
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sc->sc_txdesc[seg].hpc3_hdd_ctl:
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sc->sc_txdesc[seg].hpc1_hdd_ctl);
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printf(" hdd_descptr: 0x%08x\n",
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sc->sc_txdesc[seg].hdd_descptr);
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ifp->if_flags |= IFF_OACTIVE;
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if (sc->sc_nfreetx != ofree) {
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#if 0
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printf("%s: %d packets enqueued, first %d, INTR on %d\n",
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SQ_DPRINTF(("%s: %d packets enqueued, first %d, INTR on %d\n",
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sc->sc_dev.dv_xname, lasttx - firsttx + 1,
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firsttx, lasttx);
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#endif
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firsttx, lasttx));
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/*
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* Cause a transmit interrupt to happen on the
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* last packet we enqueued, mark it as the last
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* descriptor.
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*
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* HDD_CTL_EOPACKET && HDD_CTL_INTR cause an
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* interrupt.
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*/
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KASSERT(lasttx != -1);
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sc->sc_txdesc[lasttx].hdd_ctl |= (HDD_CTL_INTR |
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HDD_CTL_EOCHAIN);
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if (sc->hpc_regs->revision == 3) {
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sc->sc_txdesc[lasttx].hpc3_hdd_ctl |= HDD_CTL_INTR |
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HDD_CTL_EOCHAIN;
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} else {
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sc->sc_txdesc[lasttx].hpc1_hdd_ctl |= HPC1_HDD_CTL_INTR;
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sc->sc_txdesc[lasttx].hpc1_hdd_bufptr |=
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HPC1_HDD_CTL_EOCHAIN;
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}
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SQ_CDTXSYNC(sc, lasttx, 1,
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BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
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* engine, rather than mucking with the DMA state here.
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*/
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status = bus_space_read_4(sc->sc_hpct, sc->sc_hpch,
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HPC_ENETX_CTL);
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sc->hpc_regs->enetx_ctl);
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if ((status & ENETX_CTL_ACTIVE) != 0) {
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if ((status & sc->hpc_regs->enetx_ctl_active) != 0) {
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SQ_TRACE(SQ_ADD_TO_DMA, firsttx, status,
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sc->sc_nfreetx);
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sc->sc_txdesc[SQ_PREVTX(firsttx)].hdd_ctl &=
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/* NB: hpc3_hdd_ctl is also hpc1_hdd_bufptr */
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sc->sc_txdesc[SQ_PREVTX(firsttx)].hpc3_hdd_ctl &=
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~HDD_CTL_EOCHAIN;
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SQ_CDTXSYNC(sc, SQ_PREVTX(firsttx), 1,
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BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
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} else {
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SQ_TRACE(SQ_START_DMA, firsttx, status, sc->sc_nfreetx);
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch,
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HPC_ENETX_NDBP, SQ_CDTXADDR(sc, firsttx));
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sc->hpc_regs->enetx_ndbp, SQ_CDTXADDR(sc, firsttx));
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if (sc->hpc_regs->revision != 3) {
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch,
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HPC1_ENETX_CFXBP, SQ_CDTXADDR(sc, firsttx));
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch,
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HPC1_ENETX_CBP, SQ_CDTXADDR(sc, firsttx));
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}
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/* Kick DMA channel into life */
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch,
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HPC_ENETX_CTL, ENETX_CTL_ACTIVE);
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sc->hpc_regs->enetx_ctl,
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sc->hpc_regs->enetx_ctl_active);
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}
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/* Set a watchdog timer in case the chip flakes out. */
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@ -747,7 +790,8 @@ sq_watchdog(struct ifnet *ifp)
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u_int32_t status;
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struct sq_softc *sc = ifp->if_softc;
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status = bus_space_read_4(sc->sc_hpct, sc->sc_hpch, HPC_ENETX_CTL);
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status = bus_space_read_4(sc->sc_hpct, sc->sc_hpch,
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sc->hpc_regs->enetx_ctl);
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log(LOG_ERR, "%s: device timeout (prev %d, next %d, free %d, "
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"status %08x)\n", sc->sc_dev.dv_xname, sc->sc_prevtx,
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sc->sc_nexttx, sc->sc_nfreetx, status);
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@ -782,14 +826,16 @@ sq_intr(void * arg)
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int handled = 0;
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u_int32_t stat;
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stat = bus_space_read_4(sc->sc_hpct, sc->sc_hpch, HPC_ENETR_RESET);
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stat = bus_space_read_4(sc->sc_hpct, sc->sc_hpch,
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sc->hpc_regs->enetr_reset);
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if ((stat & 2) == 0) {
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printf("%s: Unexpected interrupt!\n", sc->sc_dev.dv_xname);
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return 0;
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}
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch, HPC_ENETR_RESET, 2);
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch,
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sc->hpc_regs->enetr_reset, (stat | 2));
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/*
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* If the interface isn't running, the interrupt couldn't
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@ -825,6 +871,7 @@ sq_rxintr(struct sq_softc *sc)
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int i, framelen;
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u_int8_t pktstat;
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u_int32_t status;
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u_int32_t ctl_reg;
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int new_end, orig_end;
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struct ifnet *ifp = &sc->sc_ethercom.ec_if;
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@ -832,14 +879,20 @@ sq_rxintr(struct sq_softc *sc)
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SQ_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
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/* If this is a CPU-owned buffer, we're at the end of the list */
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if (sc->sc_rxdesc[i].hdd_ctl & HDD_CTL_OWN) {
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#if 0
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if (sc->hpc_regs->revision == 3)
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ctl_reg = sc->sc_rxdesc[i].hpc3_hdd_ctl & HDD_CTL_OWN;
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else
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ctl_reg = sc->sc_rxdesc[i].hpc1_hdd_ctl &
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HPC1_HDD_CTL_OWN;
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if (ctl_reg) {
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#if defined(SQ_DEBUG)
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u_int32_t reg;
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reg = bus_space_read_4(sc->sc_hpct, sc->sc_hpch,
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HPC_ENETR_CTL);
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printf("%s: rxintr: done at %d (ctl %08x)\n",
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sc->sc_dev.dv_xname, i, reg);
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sc->hpc_regs->enetr_ctl);
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SQ_DPRINTF(("%s: rxintr: done at %d (ctl %08x)\n",
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sc->sc_dev.dv_xname, i, reg));
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#endif
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break;
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}
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@ -847,8 +900,13 @@ sq_rxintr(struct sq_softc *sc)
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count++;
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m = sc->sc_rxmbuf[i];
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framelen = m->m_ext.ext_size -
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HDD_CTL_BYTECNT(sc->sc_rxdesc[i].hdd_ctl) - 3;
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framelen = m->m_ext.ext_size - 3;
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if (sc->hpc_regs->revision == 3)
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framelen -=
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HDD_CTL_BYTECNT(sc->sc_rxdesc[i].hpc3_hdd_ctl);
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else
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framelen -=
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HPC1_HDD_CTL_BYTECNT(sc->sc_rxdesc[i].hpc1_hdd_ctl);
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/* Now sync the actual packet data */
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bus_dmamap_sync(sc->sc_dmat, sc->sc_rxmap[i], 0,
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@ -886,10 +944,8 @@ sq_rxintr(struct sq_softc *sc)
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ifp->if_ipackets++;
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#if 0
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printf("%s: sq_rxintr: buf %d len %d\n", sc->sc_dev.dv_xname,
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i, framelen);
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#endif
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SQ_DPRINTF(("%s: sq_rxintr: buf %d len %d\n",
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sc->sc_dev.dv_xname, i, framelen));
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#if NBPFILTER > 0
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if (ifp->if_bpf)
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@ -901,30 +957,33 @@ sq_rxintr(struct sq_softc *sc)
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/* If anything happened, move ring start/end pointers to new spot */
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if (i != sc->sc_nextrx) {
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/* NB: hpc3_hdd_ctl is also hpc1_hdd_bufptr */
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new_end = SQ_PREVRX(i);
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sc->sc_rxdesc[new_end].hdd_ctl |= HDD_CTL_EOCHAIN;
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sc->sc_rxdesc[new_end].hpc3_hdd_ctl |= HDD_CTL_EOCHAIN;
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SQ_CDRXSYNC(sc, new_end, BUS_DMASYNC_PREREAD |
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BUS_DMASYNC_PREWRITE);
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orig_end = SQ_PREVRX(sc->sc_nextrx);
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sc->sc_rxdesc[orig_end].hdd_ctl &= ~HDD_CTL_EOCHAIN;
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sc->sc_rxdesc[orig_end].hpc3_hdd_ctl &= ~HDD_CTL_EOCHAIN;
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SQ_CDRXSYNC(sc, orig_end, BUS_DMASYNC_PREREAD |
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BUS_DMASYNC_PREWRITE);
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sc->sc_nextrx = i;
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}
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status = bus_space_read_4(sc->sc_hpct, sc->sc_hpch, HPC_ENETR_CTL);
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status = bus_space_read_4(sc->sc_hpct, sc->sc_hpch,
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sc->hpc_regs->enetr_ctl);
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/* If receive channel is stopped, restart it... */
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if ((status & ENETR_CTL_ACTIVE) == 0) {
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if ((status & sc->hpc_regs->enetr_ctl_active) == 0) {
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/* Pass the start of the receive ring to the HPC */
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch,
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HPC_ENETR_NDBP, SQ_CDRXADDR(sc, sc->sc_nextrx));
|
||||
sc->hpc_regs->enetr_ndbp, SQ_CDRXADDR(sc, sc->sc_nextrx));
|
||||
|
||||
/* And turn on the HPC ethernet receive channel */
|
||||
bus_space_write_4(sc->sc_hpct, sc->sc_hpch, HPC_ENETR_CTL,
|
||||
ENETR_CTL_ACTIVE);
|
||||
bus_space_write_4(sc->sc_hpct, sc->sc_hpch,
|
||||
sc->hpc_regs->enetr_ctl, sc->hpc_regs->enetr_ctl_active);
|
||||
}
|
||||
|
||||
return count;
|
||||
|
|
@ -934,14 +993,22 @@ static int
|
|||
sq_txintr(struct sq_softc *sc)
|
||||
{
|
||||
int i;
|
||||
int shift = 0;
|
||||
u_int32_t status;
|
||||
u_int32_t hpc1_ready = 0;
|
||||
u_int32_t hpc3_not_ready = 1;
|
||||
struct ifnet *ifp = &sc->sc_ethercom.ec_if;
|
||||
|
||||
status = bus_space_read_4(sc->sc_hpct, sc->sc_hpch, HPC_ENETX_CTL);
|
||||
if (sc->hpc_regs->revision != 3)
|
||||
shift = 16;
|
||||
|
||||
status = bus_space_read_4(sc->sc_hpct, sc->sc_hpch,
|
||||
sc->hpc_regs->enetx_ctl) >> shift;
|
||||
|
||||
SQ_TRACE(SQ_TXINTR_ENTER, sc->sc_prevtx, status, sc->sc_nfreetx);
|
||||
|
||||
if ((status & (ENETX_CTL_ACTIVE | TXSTAT_GOOD)) == 0) {
|
||||
if ((status & ( (sc->hpc_regs->enetx_ctl_active >> shift) | TXSTAT_GOOD)) == 0) {
|
||||
/* XXX */ printf("txstat: %x\n", status);
|
||||
if (status & TXSTAT_COLL)
|
||||
ifp->if_collisions++;
|
||||
|
||||
|
|
@ -965,23 +1032,48 @@ sq_txintr(struct sq_softc *sc)
|
|||
* has gone idle.
|
||||
*/
|
||||
status = bus_space_read_4(sc->sc_hpct, sc->sc_hpch,
|
||||
HPC_ENETX_CTL);
|
||||
sc->hpc_regs->enetx_ctl) >> shift;
|
||||
|
||||
SQ_CDTXSYNC(sc, i, sc->sc_txmap[i]->dm_nsegs,
|
||||
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
|
||||
|
||||
/* If not yet transmitted, try and start DMA engine again */
|
||||
if ((sc->sc_txdesc[i].hdd_ctl & HDD_CTL_XMITDONE) == 0) {
|
||||
if ((status & ENETX_CTL_ACTIVE) == 0) {
|
||||
/*
|
||||
* If not yet transmitted, try and start DMA engine again.
|
||||
* HPC3 tags transmitted descriptors with XMITDONE whereas
|
||||
* HPC1 will not halt before sending through EOCHAIN.
|
||||
*/
|
||||
if (sc->hpc_regs->revision == 3) {
|
||||
hpc3_not_ready =
|
||||
sc->sc_txdesc[i].hpc3_hdd_ctl & HDD_CTL_XMITDONE;
|
||||
} else {
|
||||
if (hpc1_ready)
|
||||
hpc1_ready++;
|
||||
else {
|
||||
if (sc->sc_txdesc[i].hpc1_hdd_ctl &
|
||||
HPC1_HDD_CTL_EOPACKET)
|
||||
hpc1_ready = 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (hpc3_not_ready == 0 || hpc1_ready == 2) {
|
||||
if ((status & (sc->hpc_regs->enetx_ctl_active >> shift)) == 0) { // XXX
|
||||
SQ_TRACE(SQ_RESTART_DMA, i, status,
|
||||
sc->sc_nfreetx);
|
||||
|
||||
bus_space_write_4(sc->sc_hpct, sc->sc_hpch,
|
||||
HPC_ENETX_NDBP, SQ_CDTXADDR(sc, i));
|
||||
sc->hpc_regs->enetx_ndbp, SQ_CDTXADDR(sc, i));
|
||||
|
||||
if (sc->hpc_regs->revision != 3) {
|
||||
bus_space_write_4(sc->sc_hpct, sc->sc_hpch,
|
||||
HPC1_ENETX_CFXBP, SQ_CDTXADDR(sc, i));
|
||||
bus_space_write_4(sc->sc_hpct, sc->sc_hpch,
|
||||
HPC1_ENETX_CBP, SQ_CDTXADDR(sc, i));
|
||||
}
|
||||
|
||||
/* Kick DMA channel into life */
|
||||
bus_space_write_4(sc->sc_hpct, sc->sc_hpch,
|
||||
HPC_ENETX_CTL, ENETX_CTL_ACTIVE);
|
||||
sc->hpc_regs->enetx_ctl,
|
||||
sc->hpc_regs->enetx_ctl_active);
|
||||
|
||||
/*
|
||||
* Set a watchdog timer in case the chip
|
||||
|
|
@ -1032,12 +1124,12 @@ void
|
|||
sq_reset(struct sq_softc *sc)
|
||||
{
|
||||
/* Stop HPC dma channels */
|
||||
bus_space_write_4(sc->sc_hpct, sc->sc_hpch, HPC_ENETR_CTL, 0);
|
||||
bus_space_write_4(sc->sc_hpct, sc->sc_hpch, HPC_ENETX_CTL, 0);
|
||||
bus_space_write_4(sc->sc_hpct, sc->sc_hpch, sc->hpc_regs->enetr_ctl, 0);
|
||||
bus_space_write_4(sc->sc_hpct, sc->sc_hpch, sc->hpc_regs->enetx_ctl, 0);
|
||||
|
||||
bus_space_write_4(sc->sc_hpct, sc->sc_hpch, HPC_ENETR_RESET, 3);
|
||||
bus_space_write_4(sc->sc_hpct, sc->sc_hpch, sc->hpc_regs->enetr_reset, 3);
|
||||
delay(20);
|
||||
bus_space_write_4(sc->sc_hpct, sc->sc_hpch, HPC_ENETR_RESET, 0);
|
||||
bus_space_write_4(sc->sc_hpct, sc->sc_hpch, sc->hpc_regs->enetr_reset, 0);
|
||||
}
|
||||
|
||||
/* sq_add_rxbuf: Add a receive buffer to the indicated descriptor. */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: sqvar.h,v 1.4 2002/05/02 20:31:19 rafal Exp $ */
|
||||
/* $NetBSD: sqvar.h,v 1.5 2003/12/30 23:48:07 sekiya Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001 Rafal K. Boni
|
||||
|
|
@ -127,49 +127,54 @@ struct sq_softc {
|
|||
#if NRND > 0
|
||||
rndsource_element_t rnd_source; /* random source */
|
||||
#endif
|
||||
struct hpc_values *hpc_regs; /* HPC register definitions */
|
||||
};
|
||||
|
||||
#define SQ_CDTXADDR(sc, x) ((sc)->sc_cddma + SQ_CDTXOFF((x)))
|
||||
#define SQ_CDRXADDR(sc, x) ((sc)->sc_cddma + SQ_CDRXOFF((x)))
|
||||
|
||||
#define SQ_CDTXSYNC(sc, x, n, ops) \
|
||||
do { \
|
||||
int __x, __n; \
|
||||
\
|
||||
__x = (x); \
|
||||
__n = (n); \
|
||||
\
|
||||
/* If it will wrap around, sync to the end of the ring. */ \
|
||||
if ((__x + __n) > SQ_NTXDESC) { \
|
||||
bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cdmap, \
|
||||
SQ_CDTXOFF(__x), sizeof(struct hpc_dma_desc) * \
|
||||
(SQ_NTXDESC - __x), (ops)); \
|
||||
__n -= (SQ_NTXDESC - __x); \
|
||||
__x = 0; \
|
||||
} \
|
||||
\
|
||||
/* Now sync whatever is left. */ \
|
||||
bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cdmap, \
|
||||
SQ_CDTXOFF(__x), sizeof(struct hpc_dma_desc) * __n, (ops)); \
|
||||
} while (0)
|
||||
static inline void
|
||||
SQ_CDTXSYNC(struct sq_softc *sc, int __x, int __n, int ops)
|
||||
{
|
||||
/* If it will wrap around, sync to the end of the ring. */
|
||||
if ((__x + __n) > SQ_NTXDESC) {
|
||||
bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cdmap,
|
||||
SQ_CDTXOFF(__x), sizeof(struct hpc_dma_desc) *
|
||||
(SQ_NTXDESC - __x), (ops));
|
||||
__n -= (SQ_NTXDESC - __x);
|
||||
__x = 0;
|
||||
}
|
||||
|
||||
/* Now sync whatever is left. */
|
||||
bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cdmap,
|
||||
SQ_CDTXOFF(__x), sizeof(struct hpc_dma_desc) * __n, (ops));
|
||||
}
|
||||
|
||||
#define SQ_CDRXSYNC(sc, x, ops) \
|
||||
bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cdmap, \
|
||||
SQ_CDRXOFF((x)), sizeof(struct hpc_dma_desc), (ops))
|
||||
|
||||
#define SQ_INIT_RXDESC(sc, x) \
|
||||
do { \
|
||||
struct hpc_dma_desc* __rxd = &(sc)->sc_rxdesc[(x)]; \
|
||||
struct mbuf *__m = (sc)->sc_rxmbuf[(x)]; \
|
||||
\
|
||||
__m->m_data = __m->m_ext.ext_buf; \
|
||||
__rxd->hdd_bufptr = (sc)->sc_rxmap[(x)]->dm_segs[0].ds_addr; \
|
||||
__rxd->hdd_descptr = SQ_CDRXADDR((sc), SQ_NEXTRX((x))); \
|
||||
__rxd->hdd_ctl = \
|
||||
__m->m_ext.ext_size | HDD_CTL_INTR | HDD_CTL_EOPACKET | \
|
||||
HDD_CTL_OWN | ((x) == (SQ_NRXDESC - 1) ? \
|
||||
HDD_CTL_EOCHAIN : 0); \
|
||||
SQ_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);\
|
||||
} while (0)
|
||||
static inline void
|
||||
SQ_INIT_RXDESC(struct sq_softc *sc, unsigned int x)
|
||||
{
|
||||
struct hpc_dma_desc* __rxd = &(sc)->sc_rxdesc[(x)];
|
||||
struct mbuf *__m = (sc)->sc_rxmbuf[(x)];
|
||||
|
||||
__m->m_data = __m->m_ext.ext_buf;
|
||||
if (sc->hpc_regs->revision == 3) {
|
||||
__rxd->hpc3_hdd_bufptr =
|
||||
(sc)->sc_rxmap[(x)]->dm_segs[0].ds_addr;
|
||||
__rxd->hpc3_hdd_ctl = __m->m_ext.ext_size | HDD_CTL_OWN |
|
||||
HDD_CTL_INTR | HDD_CTL_EOPACKET |
|
||||
((x) == (SQ_NRXDESC - 1) ? HDD_CTL_EOCHAIN : 0);
|
||||
} else {
|
||||
__rxd->hpc1_hdd_bufptr = (sc)->sc_rxmap[(x)]->dm_segs[0].ds_addr
|
||||
| ((x) == (SQ_NRXDESC - 1) ? HPC1_HDD_CTL_EOCHAIN : 0);
|
||||
__rxd->hpc1_hdd_ctl = __m->m_ext.ext_size | HPC1_HDD_CTL_OWN |
|
||||
HPC1_HDD_CTL_INTR | HPC1_HDD_CTL_EOPACKET;
|
||||
}
|
||||
__rxd->hdd_descptr = SQ_CDRXADDR((sc), SQ_NEXTRX((x)));
|
||||
SQ_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
|
||||
}
|
||||
|
||||
#endif /* _ARCH_SGIMIPS_HPC_SQVAR_H_ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue