Add pic (memory controller for IP12) driver. Originally written by
Steve Rumble, with mostly stylistic changes by myself.
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sekiya
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/* $NetBSD: pic.c,v 1.1 2004/01/12 12:07:06 sekiya Exp $ */
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/*
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* Copyright (c) 2002 Steve Rumble
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/device.h>
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#include <sys/systm.h>
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#include <machine/cpu.h>
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#include <machine/locore.h>
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#include <machine/autoconf.h>
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#include <machine/bus.h>
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#include <machine/machtype.h>
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#include <sgimips/dev/picreg.h>
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#include "locators.h"
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struct pic_softc {
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struct device sc_dev;
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bus_space_tag_t iot;
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bus_space_handle_t ioh;
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};
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static int pic_match(struct device *, struct cfdata *, void *);
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static void pic_attach(struct device *, struct device *, void *);
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static int pic_print(void *, const char *);
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void pic_bus_reset(void);
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void pic_watchdog_tickle(void);
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CFATTACH_DECL(pic, sizeof(struct pic_softc),
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pic_match, pic_attach, NULL, NULL);
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struct pic_attach_args {
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const char *iaa_name;
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bus_space_tag_t iaa_st;
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bus_space_handle_t iaa_sh;
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};
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static struct pic_softc psc;
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static int
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pic_match(struct device * parent, struct cfdata * match, void *aux)
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{
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/*
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* PIC exists on IP12 systems. It appears to be the immediate
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* ancestor of the mc, for mips1 processors.
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*/
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if (mach_type != MACH_SGI_IP12)
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return (0);
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return (1);
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}
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static void
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pic_attach(struct device * parent, struct device * self, void *aux)
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{
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u_int32_t reg;
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char picstr[80] = "";
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struct pic_attach_args iaa;
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struct mainbus_attach_args *ma = aux;
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psc.iot = SGIMIPS_BUS_SPACE_HPC;
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if (bus_space_map(psc.iot, ma->ma_addr, 0,
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BUS_SPACE_MAP_LINEAR, &psc.ioh))
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panic("pic_attach: could not allocate memory\n");
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reg = bus_space_read_4(psc.iot, psc.ioh, PIC_SYSID);
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reg = (reg >> PIC_SYSID_REVSHIFT) & PIC_SYSID_REVMASK;
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printf("\npic0: Revision %c", reg + 65);
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/* enable refresh, set big-endian, memory parity, allow slave access */
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reg = bus_space_read_4(psc.iot, psc.ioh, PIC_CPUCTRL);
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reg |= (PIC_CPUCTRL_REFRESH | PIC_CPUCTRL_BIGENDIAN | PIC_CPUCTRL_MPR |
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PIC_CPUCTRL_SLAVE);
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bus_space_write_4(psc.iot, psc.ioh, PIC_CPUCTRL, reg);
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/* query the mode register to see what's going on */
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reg = bus_space_read_4(psc.iot, psc.ioh, PIC_MODE);
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printf(": dblk (0x%x), iblk (0x%x)\n", reg & PIC_MODE_DBSIZ,
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reg & PIC_MODE_IBSIZ);
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if (reg & PIC_MODE_NOCACHE)
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strcat(picstr, "cache disabled");
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else
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strcat(picstr, "cache enabled");
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if (reg & PIC_MODE_ISTREAM)
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strcat(picstr, ", instr streaming");
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if (reg & PIC_MODE_STOREPARTIAL)
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strcat(picstr, ", store partial");
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if (reg & PIC_MODE_BUSDRIVE)
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strcat(picstr, ", bus drive");
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printf("pic0: %s", picstr);
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/* gio32 allow master, real time devices */
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reg = bus_space_read_4(psc.iot, psc.ioh, PIC_GIO32ARB_SLOT0);
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reg &= ~(PIC_GIO32ARB_SLOT_SLAVE | PIC_GIO32ARB_SLOT_LONG);
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bus_space_write_4(psc.iot, psc.ioh, PIC_GIO32ARB_SLOT0, reg);
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reg = bus_space_read_4(psc.iot, psc.ioh, PIC_GIO32ARB_SLOT1);
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reg &= ~(PIC_GIO32ARB_SLOT_SLAVE | PIC_GIO32ARB_SLOT_LONG);
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bus_space_write_4(psc.iot, psc.ioh, PIC_GIO32ARB_SLOT1, reg);
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/* default gio32 burst time */
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bus_space_write_4(psc.iot, psc.ioh, PIC_GIO32ARB_BURST,
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PIC_GIO32ARB_DEFBURST);
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/* default gio32 delay time */
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bus_space_write_4(psc.iot, psc.ioh, PIC_GIO32ARB_DELAY,
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PIC_GIO32ARB_DEFDELAY);
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printf("\n");
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/* XXX gio only on IP12 Indigo (?). does pic exist anywhere else? */
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iaa.iaa_name = "gio";
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(void) config_found(self, (void *) &iaa, pic_print);
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/* Enable watchdog, reset it */
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reg = bus_space_read_4(psc.iot, psc.ioh, PIC_CPUCTRL)
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| (PIC_CPUCTRL_WDOG);
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bus_space_write_4(psc.iot, psc.ioh, PIC_CPUCTRL, reg);
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}
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static int
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pic_print(void *aux, const char *name)
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{
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struct pic_attach_args *iaa = aux;
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if (name)
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aprint_normal("%s at %s", iaa->iaa_name, name);
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return UNCONF;
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}
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void
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pic_bus_reset(void)
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{
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bus_space_write_4(psc.iot, psc.ioh, PIC_PARITY_ERROR, 0);
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}
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void
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pic_watchdog_tickle(void)
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{
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u_int32_t reg;
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reg = bus_space_read_4(psc.iot, psc.ioh, PIC_CPUCTRL)
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& ~(PIC_CPUCTRL_WDOG);
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bus_space_write_4(psc.iot, psc.ioh, PIC_CPUCTRL, reg);
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reg = bus_space_read_4(psc.iot, psc.ioh, PIC_CPUCTRL)
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| (PIC_CPUCTRL_WDOG);
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bus_space_write_4(psc.iot, psc.ioh, PIC_CPUCTRL, reg);
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}
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@ -0,0 +1,129 @@
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/* $NetBSD: picreg.h,v 1.1 2004/01/12 12:07:06 sekiya Exp $ */
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/*
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* Copyright (c) 2002 Steve Rumble
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARCH_SGIMIPS_DEV_PICREG_H_
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#define _ARCH_SGIMIPS_DEV_PICREG_H_
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#define PIC_CPUCTRL 0x00 /* CPU control */
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#define PIC_CPUCTRL_REFRESH 0x0001 /* refresh enable */
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#define PIC_CPUCTRL_BIGENDIAN 0x0002 /* big endian mode */
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#define PIC_CPUCTRL_DBREFILL 0x0004 /* data block refill */
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#define PIC_CPUCTRL_IBREFILL 0x0008 /* instruction block refill */
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#define PIC_CPUCTRL_GDMAINTR 0x0010 /* gfx intr on completion */
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#define PIC_CPUCTRL_GDMASYNC 0x0020 /* gfx dma sync */
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#define PIC_CPUCTRL_FREFRESH 0x0040 /* fast refresh on 33mhz+ gio */
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#define PIC_CPUCTRL_NOVMEERR 0x0080 /* disables vme bus errors */
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#define PIC_CPUCTRL_FREFRESHB 0x0080 /* fast refresh on revs. a+b */
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#define PIC_CPUCTRL_GR2 0x0100 /* gio gr2 mode (?) */
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#define PIC_CPUCTRL_SYSRESET 0x0200 /* vme sysreset line */
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#define PIC_CPUCTRL_MPR 0x0400 /* memory read parity enable */
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#define PIC_CPUCTRL_SLAVE 0x0800 /* slave accesses permitted */
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#define PIC_CPUCTRL_VMEARB 0x1000 /* vme arbiter enable */
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#define PIC_CPUCTRL_WPR 0x2000 /* write bad parity */
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#define PIC_CPUCTRL_WDOG 0x4000 /* watchdog enable */
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#define PIC_CPUCTRL_GFXRESET 0x8000 /* reset graphics */
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#define PIC_MODE 0x04 /* system mode */
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#define PIC_MODE_DBSIZ 0x0003 /* data block size */
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#define PIC_MODE_IBSIZ 0x000c /* instruction block size */
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#define PIC_MODE_ISTREAM 0x0010 /* instruction streaming */
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#define PIC_MODE_NOCACHE 0x0020 /* cache disabled */
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#define PIC_MODE_STOREPARTIAL 0x0040 /* store partial */
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#define PIC_MODE_BUSDRIVE 0x0080 /* bus drive */
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#define PIC_SYSID 0x08 /* system id */
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#define PIC_SYSID_FPU 0x0001 /* fpu exists */
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#define PIC_SYSID_GDMAERR 0x0004 /* graphics dma error */
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#define PIC_SYSID_GDMADONE 0x0008 /* graphics dma complete */
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#define PIC_SYSID_VMERMW 0x0010 /* vme read-mod-write */
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#define PIC_SYSID_REVSHIFT 0x0006 /* Rev bits shifted */
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#define PIC_SYSID_REVMASK 0x0007 /* PIC revision */
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#define PIC_MEMCFG0 0x10000 /* memory config register 0 */
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#define PIC_MEMCFG1 0x10004 /* memory config register 1 */
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#define PIC_MEMCFG_4MB 0x0000 /* 4 megabytes (never occurs) */
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#define PIC_MEMCFG_8MB 0x0001 /* 8 megabytes */
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#define PIC_MEMCFG_16MB 0x0003 /* 16 megabytes */
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#define PIC_MEMCFG_32MB 0x0007 /* 32 megabytes */
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#define PIC_MEMCFG_64MB 0x000f /* 64 megabytes */
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#define PIC_MEMCFG_BADSIZ 0x0000 /* bad memory size */
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#define PIC_MEMCFG_ADDRMASK 0x003f /* memory address mask */
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#define PIC_MEMCFG_BADADDR 0x003f /* no memory in bank */
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#define PIC_MEMCFG_SIZMASK 0x0f00 /* bank size mask */
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/*
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* The bank memory address is computed the same way mc's is.
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* Size is similar, only having one less bit (max. 64MB per bank).
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*/
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#define PIC_MEMCFG_ADDR(x) \
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((x & PIC_MEMCFG_ADDRMASK) << 22)
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#define PIC_MEMCFG_SIZ(x) \
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(((x & PIC_MEMCFG_SIZMASK) + 0x100) << 14)
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#define PIC_WRONLY_REFRESH 0x10100 /* write only refresh timer */
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#define PIC_PARITY_ERROR 0x10200 /* parity errors */
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#define PIC_PARITY_ERROR_GDMA 0x0001 /* graphics dma */
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#define PIC_PARITY_ERROR_DMA 0x0002
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#define PIC_PARITY_ERROR_CPU 0x0004
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#define PIC_PARITY_ERROR_VME 0x0008
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#define PIC_PARITY_ERROR_BYTE3 0x0010 /* error in fourth byte */
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#define PIC_PARITY_ERROR_BYTE2 0x0020 /* error in third byte */
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#define PIC_PARITY_ERROR_BYTE1 0x0040 /* error in second byte */
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#define PIC_PARITY_ERROR_BYTE0 0x0080 /* error in first byte */
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#define PIC_PARITY_ADDR_CPU 0x10204 /* cpu error address */
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#define PIC_PARITY_ADDR_DMA 0x10208 /* dma error address */
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#define PIC_PARITY_ERROR_CLEAR 0x10210 /* clear parity errors */
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/*
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* GIO slot configuration registers described by the 'GIO BUS Specification'
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* apparently no IP20 counterpart on mc.
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*/
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#define PIC_GIO32ARB_SLOT0 0x20000 /* set slot 0 config */
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#define PIC_GIO32ARB_SLOT1 0x20004 /* set slot 1 config */
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#define PIC_GIO32ARB_SLOT_SLAVE 0x0001 /* slave only */
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#define PIC_GIO32ARB_SLOT_LONG 0x0002 /* long burst */
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#define PIC_GIO32ARB_BURST 0x20008 /* set gio burst */
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#define PIC_GIO32ARB_DEFBURST 0x0001 /* default burst value */
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#define PIC_GIO32ARB_DELAY 0x2000c /* set gio delay */
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#define PIC_GIO32ARB_DEFDELAY 0x00f2 /* default delay value */
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#endif /* _ARCH_SGIMIPS_DEV_PICREG_H_ */
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