Move IOC (integrated peripheral controller) init code into the IP22-specific
routine, as IP20 does not possess an IOC. This will eventually be moved into a dedicated IOC driver that attaches its peripherals as children, but the changes involved are too intrusive right now.
This commit is contained in:
sekiya
parent
3e021de39c
commit
a15d89e48a
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@ -1,4 +1,4 @@
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/* $NetBSD: ip22.c,v 1.19 2003/12/14 05:23:12 sekiya Exp $ */
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/* $NetBSD: ip22.c,v 1.20 2003/12/14 07:53:10 sekiya Exp $ */
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/*
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* Copyright (c) 2001, 2002 Rafal K. Boni
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@ -28,7 +28,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ip22.c,v 1.19 2003/12/14 05:23:12 sekiya Exp $");
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__KERNEL_RCSID(0, "$NetBSD: ip22.c,v 1.20 2003/12/14 07:53:10 sekiya Exp $");
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#include "opt_cputype.h"
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#include "opt_machtypes.h"
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@ -83,50 +83,66 @@ ip22_init(void)
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unsigned long cps;
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unsigned long ctrdiff[3];
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mach_type = MACH_SGI_IP22;
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/* enable watchdog timer, clear it */
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*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fa00004) |= 0x100;
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*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fa00014) = 0;
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sysid = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9858);
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if (sysid & 1)
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mach_subtype = MACH_SGI_IP22_FULLHOUSE;
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if ( !strcmp(cpu_model, "SGI-IP20"))
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{
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mach_type = MACH_SGI_IP20;
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int23addr = 0x1fb801c0;
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}
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else
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mach_subtype = MACH_SGI_IP22_GUINESS;
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{
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mach_type = MACH_SGI_IP22;
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sysid = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9858);
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if (sysid & 1)
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{
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mach_subtype = MACH_SGI_IP22_FULLHOUSE;
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int23addr = 0x1fbd9000;
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}
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else
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{
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mach_subtype = MACH_SGI_IP22_GUINESS;
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int23addr = 0x1fbd9880;
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}
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mach_boardrev = (sysid >> 1) & 0x0f;
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mach_boardrev = (sysid >> 1) & 0x0f;
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printf("IOC rev %d, machine %s, board rev %d\n", (sysid >> 5) & 0x07,
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(sysid & 1) ? "Indigo2 (Fullhouse)" : "Indy (Guiness)",
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(sysid >> 1) & 0x0f);
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printf("IOC rev %d, machine %s, board rev %d\n",
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(sysid >> 5) & 0x07,
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(sysid & 1) ? "Indigo2 (Fullhouse)" : "Indy (Guiness)",
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(sysid >> 1) & 0x0f);
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if (mach_subtype == MACH_SGI_IP22_FULLHOUSE)
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int23addr = 0x1fbd9000;
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else
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int23addr = 0x1fbd9880;
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/*
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* Reset Parallel port, Keyboard/mouse and EISA. Turn LED off.
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* For Fullhouse, toggle magic GIO reset bit.
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*/
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/* Reset timer interrupts */
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*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(int23addr + 0x20) = 3;
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iocreset = 0x17;
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if (mach_subtype == MACH_SGI_IP22_FULLHOUSE)
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iocreset |= 0x08;
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/*
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* Reset Parallel port, Keyboard/mouse and EISA. Turn LED off.
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* For Fullhouse, toggle magic GIO reset bit.
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*/
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iocreset = 0x17;
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if (mach_subtype == MACH_SGI_IP22_FULLHOUSE)
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iocreset |= 0x08;
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*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9870) = iocreset;
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*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9870) = iocreset;
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/*
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* Set the 10BaseT port to use UTP cable, set autoselect mode
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* for the ethernet interface (AUI vs. TP), set the two serial
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* ports to PC mode.
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*/
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/*
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* Set the 10BaseT port to use UTP cable, set autoselect mode for
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* the ethernet interface (AUI vs. TP), set the two serial ports
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* to PC mode.
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*/
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iocwrite = 0x3a;
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*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9878) = iocwrite;
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iocwrite = 0x3a;
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*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9878) = iocwrite;
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/* Set the general control registers for Guiness */
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if (mach_subtype == MACH_SGI_IP22_GUINESS) {
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*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9848) = 0xff;
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*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd984c) = 0xff;
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}
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/* Hardcode interrupts 7, 11 to mappable interrupt 0,1 handlers */
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intrtab[7].ih_fun = ip22_mappable_intr;
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intrtab[7].ih_arg = (void*) 0;
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intrtab[11].ih_fun = ip22_mappable_intr;
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intrtab[11].ih_arg = (void*) 1;
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}
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/* Clean out interrupt masks */
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*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(int23addr + 0x04) = 0x00;
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@ -135,11 +151,16 @@ ip22_init(void)
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*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(int23addr + 0x14) = 0x00;
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*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(int23addr + 0x18) = 0x00;
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/* Set the general control registers for Guiness */
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if (mach_subtype == MACH_SGI_IP22_GUINESS) {
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*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9848) = 0xff;
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*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd984c) = 0xff;
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}
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/* enable watchdog timer, clear it */
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*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fa00004) |= 0x100;
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*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fa00014) = 0;
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/* Reset timer interrupts */
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*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(int23addr + 0x20) = 3;
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platform.iointr = ip22_intr;
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platform.bus_reset = ip22_bus_reset;
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@ -150,13 +171,6 @@ ip22_init(void)
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ttymask = 0x0f00;
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clockmask = 0xbf00;
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/* Hardcode interrupts 7, 11 to mappable interrupt 0,1 handlers */
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intrtab[7].ih_fun = ip22_mappable_intr;
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intrtab[7].ih_arg = (void*) 0;
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intrtab[11].ih_fun = ip22_mappable_intr;
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intrtab[11].ih_arg = (void*) 1;
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/* Prime cache */
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ip22_cal_timer(int23addr + 0x3c, int23addr + 0x38);
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