I/O processor and the i31244 PCI-X S-ATA controller.
The IQ31244 is almost identical to the IQ80321, from software's
perspective, so we share much of the code.
baudrate, instead of a compile time constant.
+ simplify bootstrap_bs_map() by mapping all built-in peripheral
registers at start.
+ check SW3 and SW7 and toggle RB_SINGLE and RB_KDB in boothowto if
pressed.
Also in the ARM32_PMAP_NEW case, reclaim the USPACE-bytes of wasted space
at the top of the user address that hasn't been needed for a very very
long time.
LOADADDR(previous_section) + (ADDR(current_section) - ADDR(previous_section))
to avoid using SIZEOF(), which does not properly take into account
the size of orphans that might be sorted with the section.
- to identify device instance, using hardware address.
- when console accesses device, using statically mapped address.
- when tty accesses device, using handler given by bus_space_map().
no need device ixpcom in evbarm/conf/files.evbarm move it to
arm/ixp12x0/files.ixp12x0
ixp12x0_com.c:
some fix around address handling
1. Do not call bus_space_map() in ixpcominit(). Calling bus_space_map()
is not safe here, because bus_space_map() calls uvm_km_valloc() but
uvm is not yet initialized.
2. Use dv_unit to determine console instead comparering iobase.
Now you can attach ixpcom0 with physical address like this:
ixpcom* at ixpsip? addr 0x90000000 size 0x4000
Statically mapped address (0xf0000000) is still usable.
ixp12x0_clk:
1. access PLL_CFG register via bus_space
2. Make the delay() working correctly. (bug fix)
3. Start the timer device without interrupt on attach time.
Now delay() called before cpu_initclocks() works fine.
ixp12x0_pci:
1.Mapping PCI type0/1 configuration space to the upper address.
2."PCI I/O Cycle Access" mapping to same virtual address(VA==PA)
but size of this mapping increase to 1MByte because fails
cause couldnt set L2 table.
3.use bus_space address handling in ixp12x0_pci.c.
and development board, based around their BECC companion chip. Despite
its name, the board can run in big- or little-endian mode (we currently
run only in the latter).
cd ${KERNSRCDIR}/${KERNARCHDIR}/compile && ${PRINTOBJDIR}
This is far simpler than the previous system, and more robust with
objdirs built via BSDOBJDIR.
The previous method of finding KERNOBJDIR when using BSDOBJDIR by
referencing _SRC_TOP_OBJ_ from another directory was extremely
fragile due to the depth first tree walk by <bsd.subdir.mk>, and
the caching of _SRC_TOP_OBJ_ (with MAKEOVERRIDES) which would be
empty on the *first* pass to create fresh objdirs.
This change requires adding sys/arch/*/compile/Makefile to create
the objdir in that directory, and descending into arch/*/compile
from arch/*/Makefile. Remove the now-unnecessary .keep_me files
whilst here.
Per lengthy discussion with Andrew Brown.
* Define an ARM_INTR_IMPL option, which specifies a header file
describing the interrupt implementation for the platform. Use
this instead of the list of EVBARM_BOARDTYPE checks.
* Make the s3c2xx0 interrupt dispatch code a bit more generic, and move
it to a generic location so that other platforms can use it.
This eliminates all uses of the EVBARM_BOARDTYPE stuff, so delete it.
kqueue provides a stateful and efficient event notification framework
currently supported events include socket, file, directory, fifo,
pipe, tty and device changes, and monitoring of processes and signals
kqueue is supported by all writable filesystems in NetBSD tree
(with exception of Coda) and all device drivers supporting poll(2)
based on work done by Jonathan Lemon for FreeBSD
initial NetBSD port done by Luke Mewburn and Jason Thorpe
add rd, pc, #foo - . - 8 -> adr rd, foo
ldr rd, [pc, #foo - . - 8] -> ldr rd, foo
Also, when saving the return address for a function pointer call, use
"mov lr, pc" just before the call unless the return address is somewhere
other than just after the call site.
Finally, a few obvious little micro-optimisations like using LDR directly
rather than ADR followed by LDR, and loading directly into PC rather than
bouncing via R0.
attached to "obio") on the IQ80310 and IQ80321. It makes more sense
to do it this way for this type of system (the goal being to encapsulate
as much information about the board as possible into one file).
This merge changes the device switch tables from static array to
dynamically generated by config(8).
- All device switches is defined as a constant structure in device drivers.
- The new grammer ``device-major'' is introduced to ``files''.
device-major <prefix> char <num> [block <num>] [<rules>]
- All device major numbers must be listed up in port dependent majors.<arch>
by using this grammer.
- Added the new naming convention.
The name of the device switch must be <prefix>_[bc]devsw for auto-generation
of device switch tables.
- The backward compatibility of loading block/character device
switch by LKM framework is broken. This is necessary to convert
from block/character device major to device name in runtime and vice versa.
- The restriction to assign device major by LKM is completely removed.
We don't need to reserve LKM entries for dynamic loading of device switch.
- In compile time, device major numbers list is packed into the kernel and
the LKM framework will refer it to assign device major number dynamically.
to do uncached memory access during VM operations (which can be
quite expensive on some CPUs).
We currently write-back PTEs as soon as they're modified; there is
some room for optimization (to write them back in larger chunks).
For PTEs in the APTE space (i.e. PTEs for pmaps that describe another
process's address space), PTEs must also be evicted from the cache
complete (PTEs in PTE space will be evicted durint a context switch).
Change the bus_dmamap_sync() macro to test the ops argument against pre-
and post- constants. The compiler will optimize out dead code because
of the constants. Since post- operations are not needed on ARM (except
for ISA bounce buffers), this eliminate a large number of function calls
which are noops, each of which cost at least 6 cycles just in the call
and return overhead (not to mention whatever other useless work the
compiler decides to do in the callee).
counters. These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.
pmc(9) is meant to be a general interface. Initially, the Intel XScale
counters are the only ones supported.
A new "arm32_dma_range" structure now describes a DMA window, with
a system address base, bus address base, and length. In addition to
providing info about which memory regions are legal for DMA, the new
structure provides address translation support, as well.
As before, if a tag does not list any ranges, then all addresses are
considered valid, and no DMA address translation is performed.
This allows us to remove a large chunk of code which was duplicated and
tweaked slightly (to do the address translation) from the stock ARM
bus_dma in the XScale IOP and ARM Integrator ports.
Test compiled on all ARM platforms, test booted on Intel IQ80321 and Shark.
into platform-specific initialization code, giving platform-specific
code control over which free list a given chunk of memory gets put
onto.
Changes are essentially mechanical. Test compiled for all ARM
platforms, test booted on Intel IQ80321 and Shark.
Discussed some time ago on port-arm.
the virtual address for each DMA segment, just cache a pointer to the
original buffer/buftype used to load the DMA map, and use that. This
lets us shrink the bus_dma_segment_t down from 12 bytes to 8, and the
cache flushing is also more efficient.
Tested on an i80321 -- changes to others are mechanical.
