Add a new option EVBARM_BOARDTYPE to differentiate between different
evbarm ports. Inline _splraise/_spllower/splx for i80321 and iq80310 for more performance.
This commit is contained in:
briggs
parent
003b8e8bca
commit
126f6cf9bc
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@ -1,4 +1,4 @@
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/* $NetBSD: i80321_icu.c,v 1.4 2002/08/14 19:47:18 thorpej Exp $ */
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/* $NetBSD: i80321_icu.c,v 1.5 2002/08/17 16:42:20 briggs Exp $ */
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/*
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* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
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@ -57,13 +57,13 @@
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struct intrq intrq[NIRQ];
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/* Interrupts to mask at each level. */
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static int imask[NIPL];
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int i80321_imask[NIPL];
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/* Current interrupt priority level. */
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__volatile int current_spl_level;
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/* Interrupts pending. */
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static __volatile int ipending;
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__volatile int i80321_ipending;
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/* Software copy of the IRQs we have enabled. */
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__volatile uint32_t intr_enabled;
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@ -155,14 +155,17 @@ i80321_iintsrc_read(void)
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return (iintsrc & intr_enabled);
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}
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#if defined(EVBARM_SPL_NOINLINE)
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static __inline void
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i80321_set_intrmask(void)
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{
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extern __volatile uint32_t intr_enabled;
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__asm __volatile("mcr p6, 0, %0, c0, c0, 0"
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:
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: "r" (intr_enabled & ICU_INT_HWMASK));
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}
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#endif
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static __inline void
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i80321_set_intrsteer(void)
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@ -217,76 +220,76 @@ i80321_intr_calculate_masks(void)
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if (intrq[irq].iq_levels & (1U << ipl))
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irqs |= (1U << irq);
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}
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imask[ipl] = irqs;
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i80321_imask[ipl] = irqs;
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}
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imask[IPL_NONE] = 0;
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i80321_imask[IPL_NONE] = 0;
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/*
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* Initialize the soft interrupt masks to block themselves.
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*/
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imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFT);
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imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK);
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imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET);
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imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL);
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i80321_imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFT);
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i80321_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK);
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i80321_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET);
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i80321_imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL);
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/*
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* splsoftclock() is the only interface that users of the
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* generic software interrupt facility have to block their
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* soft intrs, so splsoftclock() must also block IPL_SOFT.
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*/
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imask[IPL_SOFTCLOCK] |= imask[IPL_SOFT];
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i80321_imask[IPL_SOFTCLOCK] |= i80321_imask[IPL_SOFT];
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/*
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* splsoftnet() must also block splsoftclock(), since we don't
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* want timer-driven network events to occur while we're
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* processing incoming packets.
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*/
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imask[IPL_SOFTNET] |= imask[IPL_SOFTCLOCK];
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i80321_imask[IPL_SOFTNET] |= i80321_imask[IPL_SOFTCLOCK];
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/*
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* Enforce a heirarchy that gives "slow" device (or devices with
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* limited input buffer space/"real-time" requirements) a better
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* chance at not dropping data.
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*/
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imask[IPL_BIO] |= imask[IPL_SOFTNET];
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imask[IPL_NET] |= imask[IPL_BIO];
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imask[IPL_SOFTSERIAL] |= imask[IPL_NET];
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imask[IPL_TTY] |= imask[IPL_SOFTSERIAL];
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i80321_imask[IPL_BIO] |= i80321_imask[IPL_SOFTNET];
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i80321_imask[IPL_NET] |= i80321_imask[IPL_BIO];
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i80321_imask[IPL_SOFTSERIAL] |= i80321_imask[IPL_NET];
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i80321_imask[IPL_TTY] |= i80321_imask[IPL_SOFTSERIAL];
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/*
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* splvm() blocks all interrupts that use the kernel memory
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* allocation facilities.
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*/
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imask[IPL_IMP] |= imask[IPL_TTY];
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i80321_imask[IPL_IMP] |= i80321_imask[IPL_TTY];
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/*
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* Audio devices are not allowed to perform memory allocation
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* in their interrupt routines, and they have fairly "real-time"
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* requirements, so give them a high interrupt priority.
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*/
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imask[IPL_AUDIO] |= imask[IPL_IMP];
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i80321_imask[IPL_AUDIO] |= i80321_imask[IPL_IMP];
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/*
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* splclock() must block anything that uses the scheduler.
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*/
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imask[IPL_CLOCK] |= imask[IPL_AUDIO];
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i80321_imask[IPL_CLOCK] |= i80321_imask[IPL_AUDIO];
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/*
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* No separate statclock on the IQ80310.
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*/
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imask[IPL_STATCLOCK] |= imask[IPL_CLOCK];
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i80321_imask[IPL_STATCLOCK] |= i80321_imask[IPL_CLOCK];
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/*
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* splhigh() must block "everything".
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*/
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imask[IPL_HIGH] |= imask[IPL_STATCLOCK];
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i80321_imask[IPL_HIGH] |= i80321_imask[IPL_STATCLOCK];
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/*
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* XXX We need serial drivers to run at the absolute highest priority
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* in order to avoid overruns, so serial > high.
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*/
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imask[IPL_SERIAL] |= imask[IPL_HIGH];
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i80321_imask[IPL_SERIAL] |= i80321_imask[IPL_HIGH];
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/*
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* Now compute which IRQs must be blocked when servicing any
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@ -299,12 +302,12 @@ i80321_intr_calculate_masks(void)
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i80321_enable_irq(irq);
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for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
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ih = TAILQ_NEXT(ih, ih_list))
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irqs |= imask[ih->ih_ipl];
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irqs |= i80321_imask[ih->ih_ipl];
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iq->iq_mask = irqs;
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}
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}
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static void
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__inline void
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i80321_do_pending(void)
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{
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static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED;
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@ -318,9 +321,9 @@ i80321_do_pending(void)
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oldirqstate = disable_interrupts(I32_bit);
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#define DO_SOFTINT(si) \
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if ((ipending & ~new) & SI_TO_IRQBIT(si)) { \
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ipending &= ~SI_TO_IRQBIT(si); \
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current_spl_level |= imask[si_to_ipl[(si)]]; \
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if ((i80321_ipending & ~new) & SI_TO_IRQBIT(si)) { \
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i80321_ipending &= ~SI_TO_IRQBIT(si); \
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current_spl_level |= i80321_imask[si_to_ipl[(si)]]; \
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restore_interrupts(oldirqstate); \
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softintr_dispatch(si); \
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oldirqstate = disable_interrupts(I32_bit); \
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@ -337,16 +340,7 @@ i80321_do_pending(void)
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restore_interrupts(oldirqstate);
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}
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int
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_splraise(int ipl)
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{
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int old;
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old = current_spl_level;
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current_spl_level |= imask[ipl];
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return (old);
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}
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#if defined(EVBARM_SPL_NOINLINE)
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__inline void
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splx(int new)
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@ -355,12 +349,7 @@ splx(int new)
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current_spl_level = new;
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/*
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* If there are pending HW interrupts which are being
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* unmasked, then enable them in the INTCTL register.
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* This will cause them to come flooding in.
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*/
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hwpend = (ipending & ICU_INT_HWMASK) & ~new;
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hwpend = (i80321_ipending & ICU_INT_HWMASK) & ~new;
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if (hwpend != 0) {
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oldirqstate = disable_interrupts(I32_bit);
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intr_enabled |= hwpend;
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@ -368,31 +357,66 @@ splx(int new)
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restore_interrupts(oldirqstate);
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}
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/* If there are software interrupts to process, do it. */
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if ((ipending & INT_SWMASK) & ~new)
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if ((i80321_ipending & INT_SWMASK) & ~new)
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i80321_do_pending();
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}
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int
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_splraise(int ipl)
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{
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int old;
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old = current_spl_level;
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current_spl_level |= i80321_imask[ipl];
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return (old);
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}
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int
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_spllower(int ipl)
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{
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int old = current_spl_level;
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splx(imask[ipl]);
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return (old);
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splx(i80321_imask[ipl]);
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return(old);
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}
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#else /* EVBARM_SPL_NOINLINE */
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#undef splx
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__inline void
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splx(int new)
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{
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i80321_splx(new);
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}
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#undef _spllower
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int
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_spllower(int ipl)
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{
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return i80321_spllower(ipl);
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}
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#undef _splraise
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int
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_splraise(int ipl)
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{
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return i80321_splraise(ipl);
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}
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#endif /* else EVBARM_SPL_NOINLINE */
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void
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_setsoftintr(int si)
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{
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int oldirqstate;
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oldirqstate = disable_interrupts(I32_bit);
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ipending |= SI_TO_IRQBIT(si);
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i80321_ipending |= SI_TO_IRQBIT(si);
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restore_interrupts(oldirqstate);
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/* Process unmasked pending soft interrupts. */
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if ((ipending & INT_SWMASK) & ~current_spl_level)
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if ((i80321_ipending & INT_SWMASK) & ~current_spl_level)
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i80321_do_pending();
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}
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@ -521,11 +545,11 @@ i80321_intr_dispatch(struct clockframe *frame)
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* IRQ is masked; mark it as pending and check
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* the next one. Note: the IRQ is already disabled.
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*/
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ipending |= ibit;
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i80321_ipending |= ibit;
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continue;
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}
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ipending &= ~ibit;
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i80321_ipending &= ~ibit;
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iq = &intrq[irq];
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iq->iq_ev.ev_count++;
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@ -546,7 +570,7 @@ i80321_intr_dispatch(struct clockframe *frame)
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}
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/* Check for pendings soft intrs. */
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if ((ipending & INT_SWMASK) & ~current_spl_level) {
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if ((i80321_ipending & INT_SWMASK) & ~current_spl_level) {
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oldirqstate = enable_interrupts(I32_bit);
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i80321_do_pending();
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restore_interrupts(oldirqstate);
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@ -0,0 +1,124 @@
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/* $NetBSD: i80321_intr.h,v 1.1 2002/08/17 16:42:20 briggs Exp $ */
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/*
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* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _I80321_INTR_H_
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#define _I80321_INTR_H_
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#include <arm/armreg.h>
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#include <arm/cpufunc.h>
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#include <arm/xscale/i80321reg.h>
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#if !defined(EVBARM_SPL_NOINLINE)
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static __inline void
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i80321_set_intrmask(void)
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{
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extern __volatile uint32_t intr_enabled;
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__asm __volatile("mcr p6, 0, %0, c0, c0, 0"
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:
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: "r" (intr_enabled & ICU_INT_HWMASK));
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}
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#define INT_SWMASK \
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((1U << ICU_INT_bit26) | (1U << ICU_INT_bit22) | \
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(1U << ICU_INT_bit5) | (1U << ICU_INT_bit4))
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static __inline void
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i80321_splx(int new)
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{
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extern __volatile uint32_t intr_enabled;
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extern __volatile int current_spl_level;
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extern __volatile int i80321_ipending;
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extern void i80321_do_pending(void);
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int oldirqstate, hwpend;
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current_spl_level = new;
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hwpend = (i80321_ipending & ICU_INT_HWMASK) & ~new;
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if (hwpend != 0) {
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oldirqstate = disable_interrupts(I32_bit);
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intr_enabled |= hwpend;
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i80321_set_intrmask();
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restore_interrupts(oldirqstate);
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}
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if ((i80321_ipending & INT_SWMASK) & ~new)
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i80321_do_pending();
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}
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static __inline int
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i80321_splraise(int ipl)
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{
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extern __volatile int current_spl_level;
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extern int i80321_imask[];
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int old;
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old = current_spl_level;
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current_spl_level |= i80321_imask[ipl];
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return (old);
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}
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static __inline int
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i80321_spllower(int ipl)
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{
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extern __volatile int current_spl_level;
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extern int i80321_imask[];
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int old = current_spl_level;
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i80321_splx(i80321_imask[ipl]);
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return(old);
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}
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#define splx(new) i80321_splx(new)
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#define _spllower(ipl) i80321_spllower(ipl)
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#define _splraise(ipl) i80321_splraise(ipl)
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void _setsoftintr(int);
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#undef INT_SWMASK
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#else /* !EVBARM_SPL_NOINTR */
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int _splraise(int);
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int _spllower(int);
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void splx(int);
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void _setsoftintr(int);
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#endif /* else !EVBARM_SPL_NOINTR */
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#endif _I80321_INTR_H_
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@ -1,4 +1,4 @@
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# $NetBSD: IQ80321,v 1.9 2002/08/07 03:41:43 thorpej Exp $
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# $NetBSD: IQ80321,v 1.10 2002/08/17 16:42:21 briggs Exp $
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#
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# IQ80321 -- Intel IQ80321 Evaluation Board Kernel
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#
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@ -23,6 +23,9 @@ options CPU_XSCALE_80321 # Support the XScale core
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makeoptions COPTS="-O2 -mcpu=xscale"
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# Architecture options
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options PERFCTRS
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options XSCALE_CACHE_READ_WRITE_ALLOCATE
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options HZ=512
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# File systems
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@ -68,6 +71,7 @@ options INET6 # IPV6
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#options PPP_DEFLATE # Deflate compression support for PPP
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#options PPP_FILTER # Active filter support for PPP (requires bpf)
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#options TCP_DEBUG # Record last TCP_NDEBUG packets with SO_DEBUG
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options SOSEND_LOAN
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options NFS_BOOT_BOOTP
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options NFS_BOOT_DHCP
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@ -176,6 +180,7 @@ pseudo-device vnd 4 # disk-like interface to files
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# network pseudo-devices
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pseudo-device bpfilter 4 # Berkeley packet filter
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pseudo-device loop # network loopback
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pseudo-device kttcp # network loopback
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# miscellaneous pseudo-devices
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pseudo-device pty # pseudo-terminals
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@ -1,4 +1,4 @@
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# $NetBSD: TEAMASA_NPWR,v 1.17 2002/08/07 03:40:01 thorpej Exp $
|
||||
# $NetBSD: TEAMASA_NPWR,v 1.18 2002/08/17 16:42:21 briggs Exp $
|
||||
#
|
||||
# TEAMASA_NPWR -- Team ASA, Inc. Npwr -- XScale/IOP310-based
|
||||
# server appliance.
|
||||
|
|
@ -26,6 +26,8 @@ makeoptions COPTS="-O2 -mcpu=xscale"
|
|||
options XSCALE_CCLKCFG=7 # 600MHz
|
||||
|
||||
# Architecture options
|
||||
options PERFCTRS
|
||||
options XSCALE_CACHE_READ_WRITE_ALLOCATE
|
||||
|
||||
# File systems
|
||||
|
||||
|
|
@ -71,6 +73,7 @@ options INET6 # IPV6
|
|||
#options PPP_DEFLATE # Deflate compression support for PPP
|
||||
#options PPP_FILTER # Active filter support for PPP (requires bpf)
|
||||
#options TCP_DEBUG # Record last TCP_NDEBUG packets with SO_DEBUG
|
||||
options SOSEND_LOAN
|
||||
|
||||
options NFS_BOOT_BOOTP
|
||||
options NFS_BOOT_DHCP
|
||||
|
|
@ -192,6 +195,7 @@ pseudo-device raid 4 # RAIDframe devices
|
|||
# network pseudo-devices
|
||||
pseudo-device bpfilter 4 # Berkeley packet filter
|
||||
pseudo-device loop # network loopback
|
||||
pseudo-device kttcp
|
||||
|
||||
# miscellaneous pseudo-devices
|
||||
pseudo-device pty # pseudo-terminals
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# $NetBSD: files.evbarm,v 1.13 2002/07/20 03:09:04 ichiro Exp $
|
||||
# $NetBSD: files.evbarm,v 1.14 2002/08/17 16:42:21 briggs Exp $
|
||||
#
|
||||
# First try for arm-specific configuration info
|
||||
#
|
||||
|
|
@ -66,6 +66,7 @@ include "dev/cardbus/files.cardbus" # CARDBus device
|
|||
#
|
||||
# ARM evaluation board specific devices
|
||||
#
|
||||
defparam opt_evbarm_boardtype.h EVBARM_BOARDTYPE
|
||||
|
||||
# We need to define the Integrator's "plcom" device here since
|
||||
# it we need to generate a "plcom.h" header file for conf.c
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
# $NetBSD: std.integrator,v 1.5 2002/01/30 03:59:40 thorpej Exp $
|
||||
# $NetBSD: std.integrator,v 1.6 2002/08/17 16:42:22 briggs Exp $
|
||||
#
|
||||
# standard NetBSD/netwinder options
|
||||
# standard NetBSD/integrator options
|
||||
|
||||
machine evbarm arm
|
||||
|
||||
|
|
@ -19,3 +19,5 @@ options __OLD_INTERRUPT_CODE # XXX for now
|
|||
makeoptions LOADADDRESS="0xa0100000"
|
||||
makeoptions LINKENTRY="-e 0x10000"
|
||||
makeoptions BOARDTYPE="integrator"
|
||||
|
||||
options EVBARM_BOARDTYPE=EVBARM_BOARDTYPE_INTEGRATOR
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# $NetBSD: std.iq80310,v 1.11 2002/04/25 01:50:01 briggs Exp $
|
||||
# $NetBSD: std.iq80310,v 1.12 2002/08/17 16:42:22 briggs Exp $
|
||||
#
|
||||
# standard NetBSD/evbarm for IQ80310 options
|
||||
|
||||
|
|
@ -17,5 +17,7 @@ options ARM32
|
|||
makeoptions LOADADDRESS="0xa0200000"
|
||||
makeoptions BOARDTYPE="iq80310"
|
||||
|
||||
options EVBARM_BOARDTYPE=EVBARM_BOARDTYPE_IQ80310
|
||||
|
||||
# We need to configure the PCI bus.
|
||||
options PCI_NETBSD_CONFIGURE
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# $NetBSD: std.iq80321,v 1.2 2002/04/25 01:47:56 briggs Exp $
|
||||
# $NetBSD: std.iq80321,v 1.3 2002/08/17 16:42:22 briggs Exp $
|
||||
#
|
||||
# standard NetBSD/evbarm for IQ80321 options
|
||||
|
||||
|
|
@ -17,5 +17,7 @@ options ARM32
|
|||
makeoptions LOADADDRESS="0xa0200000"
|
||||
makeoptions BOARDTYPE="iq80321"
|
||||
|
||||
options EVBARM_BOARDTYPE=EVBARM_BOARDTYPE_I80321
|
||||
|
||||
# We need to configure the PCI bus.
|
||||
options PCI_NETBSD_CONFIGURE
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# $NetBSD: std.ixm1200,v 1.1 2002/07/15 17:13:31 ichiro Exp $
|
||||
# $NetBSD: std.ixm1200,v 1.2 2002/08/17 16:42:22 briggs Exp $
|
||||
#
|
||||
# standard NetBSD/evbarm for IXM1200 options
|
||||
|
||||
|
|
@ -17,6 +17,8 @@ options ARM32
|
|||
makeoptions LOADADDRESS="0xC0200000"
|
||||
makeoptions BOARDTYPE="ixm1200"
|
||||
|
||||
options EVBARM_BOARDTYPE=EVBARM_BOARDTYPE_IXM1200
|
||||
|
||||
# We need to configure the PCI bus.
|
||||
options PCI_NETBSD_CONFIGURE
|
||||
#options __OLD_INTERRUPT_CODE # XXX XXX for now
|
||||
|
|
|
|||
|
|
@ -1,3 +1,14 @@
|
|||
/* $NetBSD: cpu.h,v 1.1 2001/11/25 15:56:03 thorpej Exp $ */
|
||||
/* $NetBSD: cpu.h,v 1.2 2002/08/17 16:42:22 briggs Exp $ */
|
||||
|
||||
#if defined(_KERNEL) && !defined(_LKM)
|
||||
|
||||
#include "opt_evbarm_boardtype.h"
|
||||
|
||||
#define EVBARM_BOARDTYPE_INTEGRATOR 1
|
||||
#define EVBARM_BOARDTYPE_IQ80310 2
|
||||
#define EVBARM_BOARDTYPE_I80321 3
|
||||
#define EVBARM_BOARDTYPE_IXM1200 4
|
||||
|
||||
#endif
|
||||
|
||||
#include <arm/cpu.h>
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: intr.h,v 1.7 2002/01/30 03:59:41 thorpej Exp $ */
|
||||
/* $NetBSD: intr.h,v 1.8 2002/08/17 16:42:22 briggs Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001 Wasabi Systems, Inc.
|
||||
|
|
@ -85,10 +85,66 @@
|
|||
#include <sys/device.h>
|
||||
#include <sys/queue.h>
|
||||
|
||||
int _splraise(int); /* provided by BSP */
|
||||
int _spllower(int); /* provided by BSP */
|
||||
void splx(int); /* provided by BSP */
|
||||
void _setsoftintr(int); /* provided by BSP */
|
||||
#if defined(_LKM)
|
||||
|
||||
int _splraise(int);
|
||||
int _spllower(int);
|
||||
void splx(int);
|
||||
void _setsoftintr(int);
|
||||
|
||||
#else /* _LKM */
|
||||
|
||||
#if defined(EVBARM_BOARDTYPE)
|
||||
|
||||
#include <machine/cpu.h>
|
||||
|
||||
/*
|
||||
* Each board needs to define the following functions:
|
||||
*
|
||||
* int _splraise(int);
|
||||
* int _spllower(int);
|
||||
* void splx(int);
|
||||
* void _setsoftintr(int);
|
||||
*
|
||||
* These may be defined as functions, static __inline functions, or macros,
|
||||
* but there must be a _spllower() and splx() defined as functions callable
|
||||
* from assembly language (for cpu_switch()). However, since it's quite
|
||||
* useful to be able to inline splx(), you could do something like the
|
||||
* following:
|
||||
*
|
||||
* in <boardtype>_intr.h:
|
||||
* static __inline int
|
||||
* boardtype_splx(int spl)
|
||||
* {...}
|
||||
*
|
||||
* #define splx(nspl) boardtype_splx(nspl)
|
||||
* ...
|
||||
* and in boardtype's machdep code:
|
||||
*
|
||||
* ...
|
||||
* #undef splx
|
||||
* int
|
||||
* splx(int spl)
|
||||
* {
|
||||
* return boardtype_splx(spl);
|
||||
* }
|
||||
*/
|
||||
|
||||
#if EVBARM_BOARDTYPE == EVBARM_BOARDTYPE_IQ80310
|
||||
#include <arch/evbarm/iq80310/iq80310_intr.h>
|
||||
#elif EVBARM_BOARDTYPE == EVBARM_BOARDTYPE_I80321
|
||||
#include <arch/arm/xscale/i80321_intr.h>
|
||||
#elif EVBARM_BOARDTYPE == EVBARM_BOARDTYPE_IXM1200
|
||||
#include <arch/evbarm/ixm1200/ixm1200_intr.h>
|
||||
#endif
|
||||
|
||||
#else /* EVBARM_BOARDTYPE */
|
||||
|
||||
#error EVBARM_BOARDTYPE not defined.
|
||||
|
||||
#endif /* else EVBARM_BOARDTYPE */
|
||||
|
||||
#endif /* else _LKM */
|
||||
|
||||
#define splhigh() _splraise(IPL_HIGH)
|
||||
#define splsoft() _splraise(IPL_SOFT)
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: iq80310_intr.c,v 1.16 2002/08/14 19:48:04 thorpej Exp $ */
|
||||
/* $NetBSD: iq80310_intr.c,v 1.17 2002/08/17 16:42:23 briggs Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
|
||||
|
|
@ -57,37 +57,17 @@
|
|||
#include <evbarm/iq80310/iq80310var.h>
|
||||
#include <evbarm/iq80310/obiovar.h>
|
||||
|
||||
#if defined(IOP310_TEAMASA_NPWR)
|
||||
/*
|
||||
* We have 5 interrupt source bits -- all in XINT3. All interrupts
|
||||
* can be masked in the CPLD.
|
||||
*/
|
||||
#define IRQ_BITS 0x1f
|
||||
#define IRQ_BITS_ALWAYS_ON 0x00
|
||||
#else /* Default to stock IQ80310 */
|
||||
/*
|
||||
* We have 8 interrupt source bits -- 5 in the XINT3 register, and 3
|
||||
* in the XINT0 register (the upper 3). Note that the XINT0 IRQs
|
||||
* (SPCI INTA, INTB, and INTC) are always enabled, since they can not
|
||||
* be masked out in the CPLD (it provides only status, not masking,
|
||||
* for those interrupts).
|
||||
*/
|
||||
#define IRQ_BITS 0xff
|
||||
#define IRQ_BITS_ALWAYS_ON 0xe0
|
||||
#define IRQ_READ_XINT0 1 /* XXX only if board rev >= F */
|
||||
#endif /* list of IQ80310-based designs */
|
||||
|
||||
/* Interrupt handler queues. */
|
||||
struct intrq intrq[NIRQ];
|
||||
|
||||
/* Interrupts to mask at each level. */
|
||||
static int imask[NIPL];
|
||||
int iq80310_imask[NIPL];
|
||||
|
||||
/* Current interrupt priority level. */
|
||||
__volatile int current_spl_level;
|
||||
|
||||
/* Interrupts pending. */
|
||||
static __volatile int ipending;
|
||||
__volatile int iq80310_ipending;
|
||||
|
||||
/* Software copy of the IRQs we have enabled. */
|
||||
uint32_t intr_enabled;
|
||||
|
|
@ -182,76 +162,76 @@ iq80310_intr_calculate_masks(void)
|
|||
if (intrq[irq].iq_levels & (1U << ipl))
|
||||
irqs |= (1U << irq);
|
||||
}
|
||||
imask[ipl] = irqs;
|
||||
iq80310_imask[ipl] = irqs;
|
||||
}
|
||||
|
||||
imask[IPL_NONE] = 0;
|
||||
iq80310_imask[IPL_NONE] = 0;
|
||||
|
||||
/*
|
||||
* Initialize the soft interrupt masks to block themselves.
|
||||
*/
|
||||
imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFT);
|
||||
imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK);
|
||||
imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET);
|
||||
imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL);
|
||||
iq80310_imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFT);
|
||||
iq80310_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK);
|
||||
iq80310_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET);
|
||||
iq80310_imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL);
|
||||
|
||||
/*
|
||||
* splsoftclock() is the only interface that users of the
|
||||
* generic software interrupt facility have to block their
|
||||
* soft intrs, so splsoftclock() must also block IPL_SOFT.
|
||||
*/
|
||||
imask[IPL_SOFTCLOCK] |= imask[IPL_SOFT];
|
||||
iq80310_imask[IPL_SOFTCLOCK] |= iq80310_imask[IPL_SOFT];
|
||||
|
||||
/*
|
||||
* splsoftnet() must also block splsoftclock(), since we don't
|
||||
* want timer-driven network events to occur while we're
|
||||
* processing incoming packets.
|
||||
*/
|
||||
imask[IPL_SOFTNET] |= imask[IPL_SOFTCLOCK];
|
||||
iq80310_imask[IPL_SOFTNET] |= iq80310_imask[IPL_SOFTCLOCK];
|
||||
|
||||
/*
|
||||
* Enforce a heirarchy that gives "slow" device (or devices with
|
||||
* limited input buffer space/"real-time" requirements) a better
|
||||
* chance at not dropping data.
|
||||
*/
|
||||
imask[IPL_BIO] |= imask[IPL_SOFTNET];
|
||||
imask[IPL_NET] |= imask[IPL_BIO];
|
||||
imask[IPL_SOFTSERIAL] |= imask[IPL_NET];
|
||||
imask[IPL_TTY] |= imask[IPL_SOFTSERIAL];
|
||||
iq80310_imask[IPL_BIO] |= iq80310_imask[IPL_SOFTNET];
|
||||
iq80310_imask[IPL_NET] |= iq80310_imask[IPL_BIO];
|
||||
iq80310_imask[IPL_SOFTSERIAL] |= iq80310_imask[IPL_NET];
|
||||
iq80310_imask[IPL_TTY] |= iq80310_imask[IPL_SOFTSERIAL];
|
||||
|
||||
/*
|
||||
* splvm() blocks all interrupts that use the kernel memory
|
||||
* allocation facilities.
|
||||
*/
|
||||
imask[IPL_IMP] |= imask[IPL_TTY];
|
||||
iq80310_imask[IPL_IMP] |= iq80310_imask[IPL_TTY];
|
||||
|
||||
/*
|
||||
* Audio devices are not allowed to perform memory allocation
|
||||
* in their interrupt routines, and they have fairly "real-time"
|
||||
* requirements, so give them a high interrupt priority.
|
||||
*/
|
||||
imask[IPL_AUDIO] |= imask[IPL_IMP];
|
||||
iq80310_imask[IPL_AUDIO] |= iq80310_imask[IPL_IMP];
|
||||
|
||||
/*
|
||||
* splclock() must block anything that uses the scheduler.
|
||||
*/
|
||||
imask[IPL_CLOCK] |= imask[IPL_AUDIO];
|
||||
iq80310_imask[IPL_CLOCK] |= iq80310_imask[IPL_AUDIO];
|
||||
|
||||
/*
|
||||
* No separate statclock on the IQ80310.
|
||||
*/
|
||||
imask[IPL_STATCLOCK] |= imask[IPL_CLOCK];
|
||||
iq80310_imask[IPL_STATCLOCK] |= iq80310_imask[IPL_CLOCK];
|
||||
|
||||
/*
|
||||
* splhigh() must block "everything".
|
||||
*/
|
||||
imask[IPL_HIGH] |= imask[IPL_STATCLOCK];
|
||||
iq80310_imask[IPL_HIGH] |= iq80310_imask[IPL_STATCLOCK];
|
||||
|
||||
/*
|
||||
* XXX We need serial drivers to run at the absolute highest priority
|
||||
* in order to avoid overruns, so serial > high.
|
||||
*/
|
||||
imask[IPL_SERIAL] |= imask[IPL_HIGH];
|
||||
iq80310_imask[IPL_SERIAL] |= iq80310_imask[IPL_HIGH];
|
||||
|
||||
/*
|
||||
* Now compute which IRQs must be blocked when servicing any
|
||||
|
|
@ -264,12 +244,12 @@ iq80310_intr_calculate_masks(void)
|
|||
iq80310_enable_irq(irq);
|
||||
for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
|
||||
ih = TAILQ_NEXT(ih, ih_list))
|
||||
irqs |= imask[ih->ih_ipl];
|
||||
irqs |= iq80310_imask[ih->ih_ipl];
|
||||
iq->iq_mask = irqs;
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
void
|
||||
iq80310_do_soft(void)
|
||||
{
|
||||
static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED;
|
||||
|
|
@ -283,9 +263,9 @@ iq80310_do_soft(void)
|
|||
oldirqstate = disable_interrupts(I32_bit);
|
||||
|
||||
#define DO_SOFTINT(si) \
|
||||
if ((ipending & ~new) & SI_TO_IRQBIT(si)) { \
|
||||
ipending &= ~SI_TO_IRQBIT(si); \
|
||||
current_spl_level |= imask[si_to_ipl[(si)]]; \
|
||||
if ((iq80310_ipending & ~new) & SI_TO_IRQBIT(si)) { \
|
||||
iq80310_ipending &= ~SI_TO_IRQBIT(si); \
|
||||
current_spl_level |= iq80310_imask[si_to_ipl[(si)]]; \
|
||||
restore_interrupts(oldirqstate); \
|
||||
softintr_dispatch(si); \
|
||||
oldirqstate = disable_interrupts(I32_bit); \
|
||||
|
|
@ -302,13 +282,14 @@ iq80310_do_soft(void)
|
|||
restore_interrupts(oldirqstate);
|
||||
}
|
||||
|
||||
#if defined(EVBARM_SPL_NOINLINE)
|
||||
int
|
||||
_splraise(int ipl)
|
||||
{
|
||||
int old;
|
||||
|
||||
old = current_spl_level;
|
||||
current_spl_level |= imask[ipl];
|
||||
current_spl_level |= iq80310_imask[ipl];
|
||||
|
||||
return (old);
|
||||
}
|
||||
|
|
@ -322,7 +303,7 @@ splx(int new)
|
|||
current_spl_level = new;
|
||||
|
||||
/* If there are software interrupts to process, do it. */
|
||||
if ((ipending & ~IRQ_BITS) & ~new)
|
||||
if ((iq80310_ipending & ~IRQ_BITS) & ~new)
|
||||
iq80310_do_soft();
|
||||
|
||||
/*
|
||||
|
|
@ -335,7 +316,7 @@ splx(int new)
|
|||
* XXX be unblocked, because we currently lose if we
|
||||
* XXX get nested interrupts, and I don't know why yet.
|
||||
*/
|
||||
if ((new & IRQ_BITS) == 0 && (ipending & IRQ_BITS))
|
||||
if ((new & IRQ_BITS) == 0 && (iq80310_ipending & IRQ_BITS))
|
||||
i80200_intr_enable(INTCTL_IM | INTCTL_PM);
|
||||
}
|
||||
|
||||
|
|
@ -344,21 +325,45 @@ _spllower(int ipl)
|
|||
{
|
||||
int old = current_spl_level;
|
||||
|
||||
splx(imask[ipl]);
|
||||
iq80310_splx(iq80310_imask[ipl]);
|
||||
return (old);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
#undef _splraise
|
||||
int
|
||||
_splraise(int ipl)
|
||||
{
|
||||
return iq80310_splraise(ipl);
|
||||
}
|
||||
|
||||
#undef splx
|
||||
__inline void
|
||||
splx(int new)
|
||||
{
|
||||
return iq80310_splx(new);
|
||||
}
|
||||
|
||||
#undef _spllower
|
||||
int
|
||||
_spllower(int ipl)
|
||||
{
|
||||
return iq80310_spllower(ipl);
|
||||
}
|
||||
#endif
|
||||
|
||||
void
|
||||
_setsoftintr(int si)
|
||||
{
|
||||
int oldirqstate;
|
||||
|
||||
oldirqstate = disable_interrupts(I32_bit);
|
||||
ipending |= SI_TO_IRQBIT(si);
|
||||
iq80310_ipending |= SI_TO_IRQBIT(si);
|
||||
restore_interrupts(oldirqstate);
|
||||
|
||||
/* Process unmasked pending soft interrupts. */
|
||||
if ((ipending & ~IRQ_BITS) & ~current_spl_level)
|
||||
if ((iq80310_ipending & ~IRQ_BITS) & ~current_spl_level)
|
||||
iq80310_do_soft();
|
||||
}
|
||||
|
||||
|
|
@ -473,11 +478,11 @@ iq80310_intr_dispatch(struct clockframe *frame)
|
|||
* the next one. Note: external IRQs are already
|
||||
* disabled.
|
||||
*/
|
||||
ipending |= ibit;
|
||||
iq80310_ipending |= ibit;
|
||||
continue;
|
||||
}
|
||||
|
||||
ipending &= ~ibit;
|
||||
iq80310_ipending &= ~ibit;
|
||||
rv = 0;
|
||||
|
||||
iq = &intrq[irq];
|
||||
|
|
@ -505,7 +510,7 @@ iq80310_intr_dispatch(struct clockframe *frame)
|
|||
#endif
|
||||
|
||||
/* Check for pendings soft intrs. */
|
||||
if ((ipending & ~IRQ_BITS) & ~current_spl_level) {
|
||||
if ((iq80310_ipending & ~IRQ_BITS) & ~current_spl_level) {
|
||||
oldirqstate = enable_interrupts(I32_bit);
|
||||
iq80310_do_soft();
|
||||
restore_interrupts(oldirqstate);
|
||||
|
|
@ -515,6 +520,6 @@ iq80310_intr_dispatch(struct clockframe *frame)
|
|||
* If no hardware interrupts are masked, re-enable external
|
||||
* interrupts.
|
||||
*/
|
||||
if ((ipending & IRQ_BITS) == 0)
|
||||
if ((iq80310_ipending & IRQ_BITS) == 0)
|
||||
i80200_intr_enable(INTCTL_IM | INTCTL_PM);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,137 @@
|
|||
/* $NetBSD: iq80310_intr.h,v 1.1 2002/08/17 16:42:23 briggs Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed for the NetBSD Project by
|
||||
* Wasabi Systems, Inc.
|
||||
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
|
||||
* or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _IQ80310_INTR_H_
|
||||
#define _IQ80310_INTR_H_
|
||||
|
||||
#include "opt_iop310.h"
|
||||
|
||||
#include <arm/armreg.h>
|
||||
#include <arm/cpufunc.h>
|
||||
|
||||
#include <arm/xscale/i80200reg.h>
|
||||
#include <arm/xscale/i80200var.h>
|
||||
|
||||
#if defined(IOP310_TEAMASA_NPWR)
|
||||
/*
|
||||
* We have 5 interrupt source bits -- all in XINT3. All interrupts
|
||||
* can be masked in the CPLD.
|
||||
*/
|
||||
#define IRQ_BITS 0x1f
|
||||
#define IRQ_BITS_ALWAYS_ON 0x00
|
||||
#else /* Default to stock IQ80310 */
|
||||
/*
|
||||
* We have 8 interrupt source bits -- 5 in the XINT3 register, and 3
|
||||
* in the XINT0 register (the upper 3). Note that the XINT0 IRQs
|
||||
* (SPCI INTA, INTB, and INTC) are always enabled, since they can not
|
||||
* be masked out in the CPLD (it provides only status, not masking,
|
||||
* for those interrupts).
|
||||
*/
|
||||
#define IRQ_BITS 0xff
|
||||
#define IRQ_BITS_ALWAYS_ON 0xe0
|
||||
#define IRQ_READ_XINT0 1 /* XXX only if board rev >= F */
|
||||
#endif /* list of IQ80310-based designs */
|
||||
|
||||
void iq80310_do_soft(void);
|
||||
|
||||
#if !defined(EVBARM_SPL_NOINLINE)
|
||||
static __inline int
|
||||
iq80310_splraise(int ipl)
|
||||
{
|
||||
extern __volatile int current_spl_level;
|
||||
extern int iq80310_imask[];
|
||||
int old;
|
||||
|
||||
old = current_spl_level;
|
||||
current_spl_level |= iq80310_imask[ipl];
|
||||
|
||||
return (old);
|
||||
}
|
||||
|
||||
static __inline void
|
||||
iq80310_splx(int new)
|
||||
{
|
||||
extern __volatile int iq80310_ipending;
|
||||
extern __volatile int current_spl_level;
|
||||
int old;
|
||||
|
||||
old = current_spl_level;
|
||||
current_spl_level = new;
|
||||
|
||||
/* If there are software interrupts to process, do it. */
|
||||
if ((iq80310_ipending & ~IRQ_BITS) & ~new)
|
||||
iq80310_do_soft();
|
||||
|
||||
/*
|
||||
* If there are pending hardware interrupts (i.e. the
|
||||
* external interrupt is disabled in the ICU), and all
|
||||
* hardware interrupts are being unblocked, then re-enable
|
||||
* the external hardware interrupt.
|
||||
*
|
||||
* XXX We have to wait for ALL hardware interrupts to
|
||||
* XXX be unblocked, because we currently lose if we
|
||||
* XXX get nested interrupts, and I don't know why yet.
|
||||
*/
|
||||
if ((new & IRQ_BITS) == 0 && (iq80310_ipending & IRQ_BITS))
|
||||
i80200_intr_enable(INTCTL_IM | INTCTL_PM);
|
||||
}
|
||||
|
||||
static __inline int
|
||||
iq80310_spllower(int ipl)
|
||||
{
|
||||
extern __volatile int current_spl_level;
|
||||
extern int iq80310_imask[];
|
||||
int old = current_spl_level;
|
||||
|
||||
iq80310_splx(iq80310_imask[ipl]);
|
||||
return (old);
|
||||
}
|
||||
|
||||
#define _splraise(ipl) iq80310_splraise(ipl)
|
||||
#define _spllower(ipl) iq80310_spllower(ipl)
|
||||
#define splx(spl) iq80310_splx(spl)
|
||||
void _setsoftintr(int);
|
||||
#else
|
||||
|
||||
int _splraise(int);
|
||||
int _spllower(int);
|
||||
void splx(int);
|
||||
void _setsoftintr(int);
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* _IQ80310_INTR_H_ */
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
/* $NetBSD: ixm1200_intr.h,v 1.1 2002/08/17 16:42:23 briggs Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002 Wasabi Systems, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Written by Allen Briggs for Wasabi Systems, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed for the NetBSD Project by
|
||||
* Wasabi Systems, Inc.
|
||||
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
|
||||
* or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _IXM1200_INTR_H_
|
||||
#define _IXM1200_INTR_H_
|
||||
|
||||
int _splraise(int);
|
||||
int _spllower(int);
|
||||
void splx(int);
|
||||
void _setsoftintr(int);
|
||||
|
||||
#endif /* _IXM1200_INTR_H_ */
|
||||
Loading…
Reference in New Issue