Some of the stuff (e.g., rarpd, bootpd, dhcpd etc., libsa) still will
only support Ethernet. Tcpdump itself should be ok, but libpcap needs
lot of work.
For the detailed change history, look at the commit log entries for
the is-newarp branch.
MMU in boot0().
This solves the problem of cache hits after the kernel has rebooted the
machine as even with the cache off hits will occur for data/instructions
already in the cache.
cleaning calls will now be indirected throught the cpu_functions
that will have the correct function pointers for the CPU in use.
All register fixup code following aborts has been removed and
instead a call to the cpu_*abt_fixup() routine is called instead
to provide the correct fixed based on the CPU type and abort mode.
different ARM CPUS with different cache architectures for example to be
supported in a single kernel.
- All CPU/MMU/TLB specific functions are now held as function
pointers in a cpu_functions structure defined in machine/cpufunc.h
All coproc 15 accesses, TLB flushing, cache cleaning/flushing
and abort correction functions are now defined in this structure.
- cpufuncs is a global structure that is setup during initarm()
that holds all the function pointers for the booted CPU.
- A global variable 'cputype' now defines the probed cputype.
- All the existing functions for manipulating CPU specific features
have been replaced with macros defined in machine/cpufunc.h
that will call the appropriate function in the cpu_functions
structure.
- CPU functions are provided for selected CPU types (config options)
and the appropriate cpu_functions structure is chosen during
booting, based on the probed CPU type.
- All the required functions for existing CPU types (ARM6, ARM7 and
SA110) have been implemented.
space handles to describe the task file registers, aux register, 16 bit
data register and 32 bit data register.
The wdc softc structure has been moved to a separate file.
Added support for multiple attachments by separating the core of the
probe and attach functions from the mainbus probe and attach routines.
Added a new wdc flags 32_BIT so that the wd can determine 32 bit xfer
support from the wdc device.
as the only argument and cast this as appropriate now that the function
pointers to the interrupt registration functions are fully prototyped.
Use <machine/conf.h> for the declarations of the device driver entry
points.
that a unit select did not complete and needs to be retried. Selection will
be retried following a disconnection if this flag is set. The function
esc_select_unit() will set/clear this flag depending on when a selection
completed or not.
that a unit select did not complete and needs to be retried. Selection will
be retried following a disconnection if this flag is set. The function
sfas_select_unit() will set/clear this flag depending on when a selection
completed or not.
tranfer routines for use where the I/O register is multiply mapped into
a block of 8 consecutive word. This allows LDM/STM instructions to be
used to improve the read write performance.
Eliminate obsolete global kernel variable "struct timezone tz"
Add RTC_OFFSET option
Add global kernel variable rtc_offset, which is initialized by
RTC_OFFSET at kernel compile time.
on i386, x68k, mac68k, pc532 and arm32, RTC_OFFSET indicates how many
minutes west (east) of GMT the hardware RTC runs. Defaults to 0.
Places where tz variable was used to indicate this in the past have
been replaced with rtc_offset.
Add sysctl interface to rtc_offset.
Kill obsolete DST_* macros in sys/time.h
gettimeofday now always returns zeroed timezone if zone is requested.
settimeofday now ignores and logs attempts to set non-existant kernel
timezone.
cgd's alpha implementation. Bus tags now point to a structure of
function pointers to bus space routines rather than being an index to
one of several I/O methods making it simpler and more efficient in
handling many different busses and mapping schemes.
ends for irq_claim() and irq_release() that will allocate and free
memory for the irqhandler structure.
Added an irqblock array that provides a quick reference to all the
interrupts that should be blocked when a particular interrupt is
received. The irq_claim() and irq_release() functions now update the
irqblock array.
Impelemented a fix for kernel locks when opening the serial post :
Revisions A->D of the SMC FDC37GT665 Peripherial controller have
a bug in the serial port that is triggered if the FIFO is enabled
while there is a byte in the rx data register resulting in the
rx ready bit being permenantly set.
podule space.
Fixed a bug in the reading of bytes from network slot cards that prevented
the correct reading of the network slot ROM description.
config code now allows duplicable devices to be attached.
on indirect-config busses a (permanent) softc that they could share
between 'match' and 'attach' routines:
Define __BROKEN_INDIRECT_CONFIG so that old autoconfiguration
interfaces are used, until drivers are converted to use the new
interfaces (actually, converted back to use the _older_ interfaces)
which prohibit indirect configuration devices from receiving a softc
in their match routine that they can share with their attach routine.
Lets users over-ride with makeoptions COPTS="..." in kernel config files.
Leave `mandatory' flags (like -msoft-float which on m68k enforces no
FP in kernel) in CFLAGS.
These alternative macros have a workaround for the STM^ bug in revision < 3
StrongARM CPU's that causes incorrect register saving if a cache line fill
is in progress during the STM.
a podulebus.
Make sure the podulebus driver conforms to the Acorn expansion card
specification:
- Probe the podule bus using sync access cycles rather than slow access
cycles.
- Read the podulebus header/ROM using sync access cycles rather than slow
access cycles
Added support the new instructions defined in the ARM V4 Architecture
Reference manual (long multiplies, half word load and stores,
half word/byte signed loads).
Added support for the ARM810 IMB architecture defined SWIs.
Fixed bug in calculating some immediate constants.
Added support for the wfs, rfs, wfc, rfc instructions
Added support for the floating point compare instructions
Added ldf, stf, ldc and stc instructions.
Fixed mis-disassembly of some msr/mrs instructions.
The ldm and stm instructions will modify the direction identifier to
use the stack variations if the base register is r13.
code as video memory must be reserved from main memory for the display.
In addition this adds generic support for using DRAM for video memory
on all machines. All video memory accessing should use the video_memory_t
structure.
Added support for the RC7500 motherboard. The RC7500 support includes a
replacement init_arm() function. This also supports the RC7500 prom debug
monitor for debugging the kernel boot.
dumps now work so call dumpsys() following a panic.
Added support for the SA110. This mainly consists of making sure the data
cache is cleaned when appropriate and that the instruction cache is
kept in sync during the bootstrap and when signal handlers are built on
the stack.
Use a larger UND32 mode stack if we are configured for KGDB.
Remove KERNEL_PT_KSTACK references as these should have died with the
removal of double mapped kstacks eons ago.
Make sure we call doshutdownhooks() if boot is called while we are still
cold.
Cleaned up prototypes declarations.
Sorted out comment indentation.
clean and tlb flush code along with write buffer drains that are
dependant on the definition of CPU_SA110.
The memory reserved for the L1 pagetables is now wired into the memory map
during the pmap_init rather than at L1 pagetable allocation time.
The L1 pages tables are zeroed during initialisation and when they are
released rather than when they are allocated.
When searching for a free L1 page table start search at the page table
after the last one allocated rather than always starting from the first one.
Added some extra DIAGNOSTIC checks for invalidate page index numbers.
Removed some old debugging code that escaped the last clean up.
Idented comments in line with code.
The irq delivery code has been rewritten. On entry to the irq vector the
processor is switched to SVC32 mode so all interrupt routines now run
in SVC32 mode rather than IRQ32 mode. This fixes lots of irq re-enabling
problems.
Interrupt latency times are now vastly improved for high priority interrupts.
Cleaned up calling ast() before returning to USR32 mode (don't need to
mess about with trapframe copying.
Cleaned up all the comments and sorted out their indentation.
Rewritten the soft interrupt delivery code.
Added generic ARM7500 support rather than just RC7500 support.
Added support for the SA110. This cpu does not need any register fix-ups
following a data abort.
Return valid signal code values on SEGV's. See machine/signal.h for
decoding SEGV signal codes.
required during pagemove() and vmapbuf() and vunmapbuf().
The kernel and undefined mode stack checks are now guarded with
#ifdef STACKCHECKS.
Tidied up comments.
cache needs to be cleans and the instruction and data caches need to
be invalidate along with the instruction and data tlbs when
the TTB is reloaded during a context switch.
if CPU_SA110 is defined. Cache cleaning is different on the SA110 as
the cache is a write back virtual cache and is split for data and instruction.
Also the cache and tlb control instructions use different coprocessor #15
registers.
Removed suspect FPA probing code, instead use the ARM FPE to probe the FPA.
Neatened up the FPE attachment code.
Recognise StrongARM class of cpu.
Updated the fpa instruction bounce handler to expect a 4th argument
when called on an undefined trap to match recent changes made to
undefined handlers.
gwr