Provide a completely new set of cache clean and tlb flush functions
if CPU_SA110 is defined. Cache cleaning is different on the SA110 as the cache is a write back virtual cache and is split for data and instruction. Also the cache and tlb control instructions use different coprocessor #15 registers.
This commit is contained in:
mark
parent
709ebdf6ab
commit
e41dd7d935
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@ -1,12 +1,10 @@
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/* $NetBSD: coproc15.S,v 1.2 1996/06/03 21:38:05 mark Exp $ */
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/* $NetBSD: coproc15.S,v 1.3 1996/10/15 21:47:51 mark Exp $ */
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/*
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* Copyright (c) 1994 Mark Brinicombe.
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* Copyright (c) 1994-1996 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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@ -17,15 +15,15 @@
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* This product includes software developed by Mark Brinicombe.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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@ -41,10 +39,11 @@
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* Manipulation of the CPU internal coprocessor #15 registers
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*
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* Created : 29/11/94
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*
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* Based on arm/readcoproc15.S & arm/writecoproc15.S
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*/
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#include <machine/vmparam.h>
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#include <machine/cpu.h>
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lr .req r14
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pc .req r15
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@ -104,21 +103,45 @@ _cpu_control:
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_setttb:
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/* We need to flush the cache as it uses virtual addresses that are about to change */
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mcr 15, 0, r0, c7, c0, 0
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#ifndef CPU_SA110
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mcr 15, 0, r0, c7, c0, 0
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#else /* CPU_SA110 */
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mrs r3, cpsr_all
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orr r1, r3, #(I32_bit | F32_bit)
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msr cpsr_all , r1
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stmfd sp!, {r0-r3, lr}
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bl _cache_clean
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ldmfd sp!, {r0-r3, lr}
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mcr 15, 0, r0, c7, c7, 0
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mcr 15, 0, r0, c7, c10, 4
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#endif /* CPU_SA110 */
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/* Write the TTB */
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mcr 15, 0, r0, c2, c0, 0
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#ifndef CPU_SA110
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/* If we have updated the TTB we must flush the TLB */
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mcr 15, 0, r0, c5, c0, 0
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mcr 15, 0, r0, c5, c0, 0
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/* For good measure we will flush the IDC as well - do we need this */
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mcr 15, 0, r0, c7, c0, 0
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/* For good measure we will flush the IDC as well */
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mcr 15, 0, r0, c7, c0, 0
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/* Make sure that pipeline is emptied */
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mov r0, r0
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mov r0, r0
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#else /* CPU_SA110 */
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/* If we have updated the TTB we must flush the TLB */
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mcr 15, 0, r0, c8, c7, 0
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mov r0, r0
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mov r0, r0
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/* For good measure we will flush the IDC as well */
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mcr 15, 0, r0, c7, c7, 0
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/* Make sure that pipeline is emptied */
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mov r0, r0
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mov r0, r0
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msr cpsr_all , r3
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#endif /* CPU_SA110 */
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mov pc, lr
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@ -128,37 +151,230 @@ _cpu_domains:
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mcr 15, 0, r0, c3, c0, 0
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mov pc, lr
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/*
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* tlb_flush - flush the whole TLB
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* itlb_flush - flush the intstruction TLB
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* dtlb_flush - flush the data TLB
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* dtlb_purge - purge an entry from the data TLB
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*
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* cache_flush - flush whole cache (invalidate)
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* icache_flush - flush instruction cache (invalidate)
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* dcache_flush - flush data cache (invalidate)
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* dcache_purge - purge data cache entry (invalidate)
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* dcache_clean - clean data cache
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* cache_clean - clean all caches
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* sync_cache - clean cache entry
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* drain_writebuf - drains the write buffer
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* sync_caches - clean all caches
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* sync_icache - ensures the icache is in sync with dcache
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* and memory
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*/
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/*
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* Notes on the cache -
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*
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* sync_icache
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* sync_caches
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* These functions garentee that the processor caches and
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* main memory are in sync.
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* Actually they garentee that any dirty data in the
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* processor cache on entry to the functions is written
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* back to main memory and the write buffer is drained.
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* These functions also flush (invalidate) the instruction
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* cache.
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* Interrupts are enabled during this function so they
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* only garentee that dirty data on entry to the function is
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* written back and only then if the dirty locations are not
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* accessed from interrupt routines called while the
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* sync is in progress.
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*
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*
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* cache_clean
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* This function cleans the data caches, drains the write
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* buffer and then flushes the instruction and data caches.
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* Interrupts are disabled by this routine so that dirty
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* data is not added to the cache prior to the data cache
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* flush.
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*
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*
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*/
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#ifndef CPU_SA110
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.global _tlbflush
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_tlbflush:
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.global _tlb_flush
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.global _itlb_flush
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.global _dtlb_flush
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_tlb_flush:
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_itlb_flush:
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_dtlb_flush:
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mcr 15, 0, r0, c5, c0, 0
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mov pc, lr
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.global _tlbpurge
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_tlbpurge:
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.global _dtlb_purge
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_dtlb_purge:
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mcr 15, 0, r0, c6, c0, 0
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mov pc, lr
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.global _idcflush
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/* .global _cache_flush*/
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/* .global _icache_flush*/
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/* .global _dcache_flush*/
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/* .global _dcache_purge_entry*/
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/* .global _dcache_clean_entry*/
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.global _cache_clean
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_idcflush:
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_cache_flush:
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_icache_flush:
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_dcache_flush:
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_dcache_purge_entry:
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_dcache_clean_entry:
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_cache_clean:
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mcr 15, 0, r0, c7, c0, 0
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mov pc, lr
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#else
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.global _tlbflush
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.global _tlbpurge
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_tlbflush:
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_tlbpurge:
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mcr 15, 0, r0, c8, c7, 0
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.global _drain_writebuf
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.global _sync_caches
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.global _sync_cache
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.global _sync_icache
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_drain_writebuf:
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_sync_cache:
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_sync_caches:
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_sync_icache:
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mov pc, lr
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#else /* CPU_SA110 */
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.global _tlb_flush
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_tlb_flush:
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#if 0
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mrs r3, cpsr_all
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orr r0, r3, #(I32_bit)
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msr cpsr_all , r0
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.global _idcflush
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mov r0, #0xf0000000
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add r1, r0, #32768
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_idcflush:
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mcr 15, 0, r0, c7, c7, 0
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mov pc, lr
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tlb_flush_loop:
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ldr r2, [r0], #32
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teq r1, r0
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bne tlb_flush_loop
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mcr 15, 0, r0, c7, c10, 4 /* drain write buffer */
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mcr 15, 0, r0, c7, c7, 0 /* flush i+d cache */
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#endif
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mcr 15, 0, r0, c7, c10, 4 /* drain write buffer */
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mcr 15, 0, r0, c8, c7, 0 /* flush i+d tlb */
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/* msr cpsr_all , r3*/
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mov pc, lr
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/* .global _itlb_flush*/
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_itlb_flush:
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mcr 15, 0, r0, c8, c5, 0 /* flush icache */
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mov pc, lr
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/* .global _dtlb_flush*/
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_dtlb_flush:
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mcr 15, 0, r0, c8, c6, 0 /* flush dcache */
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mov pc, lr
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/* .global _dtlb_purge*/
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_dtlb_purge:
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mcr 15, 0, r0, c8, c6, 1 /* purge d tlb entry */
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mov pc, lr
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/* .global _cache_flush*/
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/* .global _icache_flush*/
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/* .global _dcache_flush*/
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/* .global _dcache_purge_entry*/
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/* .global _dcache_clean_entry*/
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.global _drain_writebuf
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_cache_flush:
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mcr 15, 0, r0, c7, c7, 0 /* flush i+d cache */
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mov pc, lr
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_icache_flush:
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mcr 15, 0, r0, c7, c5, 0 /* flush icache */
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mov pc, lr
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_dcache_flush:
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mcr 15, 0, r0, c7, c6, 0 /* flush dcache */
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mov pc, lr
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_dcache_purge_entry:
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mcr 15, 0, r0, c7, c6, 1 /* purge dcache entry */
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mov pc, lr
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_dcache_clean_entry:
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mcr 15, 0, r0, c7, c10, 1 /* clean dcache entry */
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mov pc, lr
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_drain_writebuf:
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mcr 15, 0, r0, c7, c10, 4 /* draw write buffer */
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mov pc, lr
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.global _dcache_clean
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_dcache_clean:
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mrs r3, cpsr_all
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orr r0, r3, #(I32_bit | F32_bit)
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msr cpsr_all , r0
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mov r0, #0xf0000000
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add r1, r0, #32768
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dcache_clean_loop:
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ldr r2, [r0], #32
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teq r1, r0
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bne dcache_clean_loop
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mcr 15, 0, r0, c7, c10, 4 /* drain write buffer */
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mcr 15, 0, r0, c7, c6, 0 /* flush d cache */
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msr cpsr_all , r3
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mov pc, lr
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.global _cache_clean
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_cache_clean:
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mrs r3, cpsr_all
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orr r0, r3, #(I32_bit | F32_bit)
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msr cpsr_all , r0
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mov r0, #0xf0000000
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add r1, r0, #32768
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cache_clean_loop:
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ldr r2, [r0], #32
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teq r1, r0
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bne cache_clean_loop
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mcr 15, 0, r0, c7, c10, 4 /* drain write buffer */
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mcr 15, 0, r0, c7, c7, 0 /* flush i+d cache */
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msr cpsr_all , r3
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mov pc, lr
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.global _sync_icache
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_sync_icache:
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.global _sync_caches
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_sync_caches:
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mrs r3, cpsr_all
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orr r0, r3, #(I32_bit | F32_bit)
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msr cpsr_all , r0
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mov r0, #0xf0000000
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add r1, r0, #32768
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sync_icache_loop:
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ldr r2, [r0], #32
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teq r1, r0
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bne sync_icache_loop
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mcr 15, 0, r0, c7, c10, 4 /* drain write buffer */
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mcr 15, 0, r0, c7, c5, 0 /* flush i cache */
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msr cpsr_all , r3
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mov pc, lr
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.global _sync_cache
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_sync_cache:
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mcr 15, 0, r0, c7, c10, 1 /* clean dcache entry */
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mcr 15, 0, r0, c7, c10, 4 /* drain write buffer */
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mcr 15, 0, r0, c7, c5, 0 /* flush icache */
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mov pc, lr
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#endif /* CPU_SA110 */
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