Lowered the FIFO trigger threshold to 4 for rather than 8.
Impelemented a fix for kernel locks when opening the serial post : Revisions A->D of the SMC FDC37GT665 Peripherial controller have a bug in the serial port that is triggered if the FIFO is enabled while there is a byte in the rx data register resulting in the rx ready bit being permenantly set.
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17d2a69941
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c65504baea
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@ -1,4 +1,4 @@
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/* $NetBSD: com.c,v 1.12 1996/10/16 19:32:56 ws Exp $ */
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/* $NetBSD: com.c,v 1.13 1997/01/05 19:19:57 mark Exp $ */
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/*-
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* Copyright (c) 1993, 1994, 1995, 1996
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@ -412,7 +412,8 @@ comopen(dev, flag, mode, p)
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struct tty *tp;
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int s;
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int error = 0;
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int count;
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if (unit >= com_cd.cd_ndevs)
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return ENXIO;
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sc = com_cd.cd_devs[unit];
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@ -467,7 +468,7 @@ comopen(dev, flag, mode, p)
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bus_io_write_1(bc, ioh, com_fifo,
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FIFO_DMA_MODE|FIFO_ENABLE|
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FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_8);
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FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_4);
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/* Set 16550 compatibility mode */
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bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETMODE);
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@ -492,14 +493,48 @@ comopen(dev, flag, mode, p)
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HAYESP_LOBYTE(HAYESP_RXLOWMARK));
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} else
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#endif
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if (ISSET(sc->sc_hwflags, COM_HW_FIFO))
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/*
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* This is a patch for bugged revision 1-4 SMC FDC37C665
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* I/O controllers.
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* If there is RX data pending when the FIFO in turned on
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* the RX register cannot be emptied.
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*
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* Solution:
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* Make sure FIFO is off.
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* Read pending data / int status etc.
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* Enable FIFO.
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*/
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bus_io_write_1(bc, ioh, com_fifo, 0);
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for (count = 0; count < 8; ++count)
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(void)bus_io_read_1(bc, ioh, count);
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if (ISSET(sc->sc_hwflags, COM_HW_FIFO))
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/* Set the FIFO threshold based on the receive speed. */
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bus_io_write_1(bc, ioh, com_fifo,
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FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST |
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(tp->t_ispeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8));
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/* flush any pending I/O */
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while (ISSET(bus_io_read_1(bc, ioh, com_lsr), LSR_RXRDY))
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(tp->t_ispeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_4));
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/* flush any pending I/O, just incase the fix above fails limit the looping */
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count = 1024;
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while (ISSET(bus_io_read_1(bc, ioh, com_lsr), LSR_RXRDY) && count > 0) {
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(void) bus_io_read_1(bc, ioh, com_data);
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--count;
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}
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if (count == 0) {
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/*
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* Read 1024 bytes from the serial chip and still data !
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* This means something is broken ...
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*/
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printf("com init error: lsr=%02x data=%02x\n",
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bus_io_read_1(bc, ioh, com_lsr),
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bus_io_read_1(bc, ioh, com_data));
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printf("Cannot clear serial input register\n");
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CLR(tp->t_state, TS_BUSY | TS_FLUSH);
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CLR(tp->t_state, TS_WOPEN);
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if (--comsopen == 0)
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untimeout(comsoft, NULL);
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splx(s);
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return(ENXIO);
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}
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/* you turn me on, baby */
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sc->sc_mcr = MCR_DTR | MCR_RTS;
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if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN))
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@ -1,4 +1,4 @@
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/* $NetBSD: com.c,v 1.12 1996/10/16 19:32:56 ws Exp $ */
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/* $NetBSD: com.c,v 1.13 1997/01/05 19:19:57 mark Exp $ */
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/*-
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* Copyright (c) 1993, 1994, 1995, 1996
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@ -412,7 +412,8 @@ comopen(dev, flag, mode, p)
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struct tty *tp;
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int s;
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int error = 0;
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int count;
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if (unit >= com_cd.cd_ndevs)
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return ENXIO;
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sc = com_cd.cd_devs[unit];
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@ -467,7 +468,7 @@ comopen(dev, flag, mode, p)
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bus_io_write_1(bc, ioh, com_fifo,
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FIFO_DMA_MODE|FIFO_ENABLE|
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FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_8);
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FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_4);
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/* Set 16550 compatibility mode */
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bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETMODE);
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@ -492,14 +493,48 @@ comopen(dev, flag, mode, p)
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HAYESP_LOBYTE(HAYESP_RXLOWMARK));
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} else
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#endif
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if (ISSET(sc->sc_hwflags, COM_HW_FIFO))
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/*
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* This is a patch for bugged revision 1-4 SMC FDC37C665
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* I/O controllers.
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* If there is RX data pending when the FIFO in turned on
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* the RX register cannot be emptied.
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*
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* Solution:
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* Make sure FIFO is off.
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* Read pending data / int status etc.
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* Enable FIFO.
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*/
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bus_io_write_1(bc, ioh, com_fifo, 0);
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for (count = 0; count < 8; ++count)
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(void)bus_io_read_1(bc, ioh, count);
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if (ISSET(sc->sc_hwflags, COM_HW_FIFO))
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/* Set the FIFO threshold based on the receive speed. */
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bus_io_write_1(bc, ioh, com_fifo,
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FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST |
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(tp->t_ispeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8));
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/* flush any pending I/O */
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while (ISSET(bus_io_read_1(bc, ioh, com_lsr), LSR_RXRDY))
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(tp->t_ispeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_4));
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/* flush any pending I/O, just incase the fix above fails limit the looping */
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count = 1024;
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while (ISSET(bus_io_read_1(bc, ioh, com_lsr), LSR_RXRDY) && count > 0) {
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(void) bus_io_read_1(bc, ioh, com_data);
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--count;
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}
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if (count == 0) {
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/*
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* Read 1024 bytes from the serial chip and still data !
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* This means something is broken ...
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*/
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printf("com init error: lsr=%02x data=%02x\n",
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bus_io_read_1(bc, ioh, com_lsr),
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bus_io_read_1(bc, ioh, com_data));
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printf("Cannot clear serial input register\n");
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CLR(tp->t_state, TS_BUSY | TS_FLUSH);
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CLR(tp->t_state, TS_WOPEN);
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if (--comsopen == 0)
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untimeout(comsoft, NULL);
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splx(s);
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return(ENXIO);
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}
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/* you turn me on, baby */
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sc->sc_mcr = MCR_DTR | MCR_RTS;
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if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN))
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